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<omnitechnomancer> Hmmm it seems to be just the rr_arbiter, do nested for loop for generating combinational logic cause yosys issues?
<omnitechnomancer> Does this look like reasonable SystemVerilog? https://github.com/jbush001/NyuziProcessor/blob/master/hardware/core/rr_arbiter.sv
<tnt> yosys doesn't support full SV. only a very small subset.
<omnitechnomancer> Yosys does not directly accept this because of the for loops, but the output from sv2v causes yosys to consume huge amounts of memory while 'Generating RTLIL representation for module `\rr_arbiter'.'
<omnitechnomancer> I am aware of that I mostly want to know if the way this is trying to do what it is doing is bad for yosys or if yosys is buggy about it
<tnt> I think it's a bug.
<tnt> Changing the inner loop to ( bit_idx != grant_idx[BIT_IDX_WIDTH - 1:0] ) & (bit_idx < NUM_REQUESTERS) seems to fix it.
<tnt> but ... bit_idx < NUM_REQUESTED should be pretty much always true ...
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<omnitechnomancer> Hmmmm, indeed
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<omnitechnomancer> Thanks for the help tnt
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