<Gracana>
I've been wondering about the form factor for my ecp5 module, thinking it'd be convenient to just put the connectors and IO on it that I need, but otoh modular is nice... and it occurred to me that there are standards for this stuff.
<Gracana>
I could do LVDS and HDMI, SATA, PCIe, I2C and SPI, GPIO, ...
<Gracana>
I mean I probably have enough I/O to wire up everything and I just need to make sure that it's connected appropriately for the given device standard
<Gracana>
and then anyone could take the design and slap it into whatever SMARC carrier they want
<Gracana>
Is that appealing? I think it is...
<tpw_rules>
imho the modularity on those kinds of boards frustrates me
<Gracana>
Why's that?
<tpw_rules>
idk what your goals are but for those fpga devboards with not much but a high speed connector, they may as well not have any interfaces. the breakout boards are too expensive and if the interface i'd like isn't in an easily available breakout, the connector is too expensive and dense to do a custom board for
<Gracana>
oh, yeah agreed, the weird mezzanine connectors are super expensive and difficult to deal with
<Gracana>
SMARC just uses a card edge connector, and it's kind of cool becuase your processor card can have six layers and be super dense, but then your host board only needs to be four layers and routing is easy, or you can buy a generic one for cheap
<awygle>
in general i draw a distinction between dev boards and compute modules
<Gracana>
or maybe that's not worth it and I should just make a board with common I/O devices onboard and call it a day..
<tpw_rules>
my desires stop at 0.1" 40 pin IDC. of course it's hard to run SATA over one of those but the SATA connector should be on the main board anyway
<awygle>
if you'd stick it in a project as-is, then a single e.g. SODIMM edge connector is fine. if not, you probably want to break out to the standard connectors for whatever the signal is
<tpw_rules>
yeah if it's a compute module than SMARC makes sense. i would encourage you to sell an optional breakout board with all the interfaces one would want. the nvidia jetsons are good that way
<Gracana>
at the end of the day probably nobody but me is gonna use this thing, but it's always cool to think of ways it could be made useful for other folks
<Gracana>
yeah, selling it with a default carrier board seems like a good idea
<Gracana>
I dunno, I might do that just because then I can be amibitious about what it COULD connect to, without having to actually implement all that stuff fully until I'm ready.. first carrier can just be GPIO and HDMI or something
<tpw_rules>
do pc-104 :D
<Gracana>
aww yes
<Gracana>
like 15 years ago I scrounged up a PC104 system and ran FreeBSD on it and it was super neat
<Gracana>
PC/104 Plus I guess it was
<Gracana>
iirc those headers are surprisingly expensive though
<Gracana>
gigantic four-row stacking header
<Gracana>
oh, for fabrication I bought a an aoyueioaueoa PCB preheater. I have a good hot air station and a hot plate but to do BGAs I figured I either need a preheater or an oven, and I figured a preheater will be more widely useful.
<Gracana>
I nevermind, I could have sworn it was Aoyue. I bought my first iron from them and they make pretty good stuff.
<Gracana>
I looked at building my own case with PID controller and a ceramic heating element and board holder and by the time I put it all together, it's A) tricky to build, B) not necessarily any better than the Chinese device, and C) more expensive
<Gracana>
I'm envious of all the manufacturing that goes on in China. So many parts, so many tools...
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<omnitechnomancer>
I think people often repurpose toaster ovens with a PID controller as a cheap reflow oven
<Lofty>
I just want to check my understanding of Verilog's behaviour here: this would require the memory read to wait until the memory write, right?
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<ktemkin>
it’s not really about “waiting” as much as that = injects a semantic point where values are resolved
<ktemkin>
which means the lines after the “blocking assignment” act as though the new value has already been taken on
<ktemkin>
in your case, that means if `we` is high, you always get `di` on `do`
<ktemkin>
so it basically builds a mux, there
<ktemkin>
(note that I say “a point where values” are resolved and not “value”; theoretically at that point it’d resolve any previous “non-blocking” assignments for lines after as well, which creates a mess)
<ktemkin>
✨verilog ✨
<keesj>
TD-Linux: on the quickfeather?
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<Gracana>
ktemkin: Huh, I think I've read about that before but internalized it as "don't mix blocking and non-blocking assignments" and forgot what happened when you mixed them. What a mess.
<omnitechnomancer>
To me Verilog feels like someone saw Undefined behaviour and other footguns in C/C++ and decided they needed a hardware description language like that
<whitequark>
there's a good paper on the history of verilog that you might find interesting
<omnitechnomancer>
I am concerned by all the arrows in the diagram in the introduction that come from C, C++ and Java
<whitequark>
i mean yes, verilog is bad
<whitequark>
the reason i linked the paper to you is because it explains why and how it looks the way it does
<whitequark>
learn from the mistakes of the past to avoid them
<whitequark>
this is the entire point behind HOPL
<omnitechnomancer>
HOPL?
<whitequark>
"history of programming languages". it's a publication that chases down the people who designed popular languages (which usually means lots of mistakes and lots of decisions we'd do differently today) and gets them to explain why they did it
<omnitechnomancer>
I presume many issues also spring from most of these languages not having been designed primarily with synthesis in mind
<omnitechnomancer>
Ah
<whitequark>
the C++ one really goes into detail on why C++ is... like that
<whitequark>
recommended reading
<whitequark>
re synthesis: I thought so, but no, apparently Verilog was actually designed with synthesis in mind
<whitequark>
> Moorby was tasked with developing a new language and simulator to support logic
<whitequark>
verification, fault simulation, timing analysis, and synthesis. This new language was named Verilog
<omnitechnomancer>
hmmm
<Gracana>
Wow, "RTL" goes back to 1956.
<omnitechnomancer>
Sounds like a bunch of the strangeness of synthesis differences came from when Synopsys were trying to actually use it for synthesis and had to define the synthesisable subset
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<sorear>
this paper is much newer than I thought
<whitequark>
yes
<whitequark>
that's kinda how HOPL works
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<sorear>
they took exceptions from ML?!
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<ktemkin>
the way Verilog and VHDL came about makes a lot of sense, from a historic perspective; the story of how they came into their modern use is a bit more harrowing
<ktemkin>
whitequark: thanks for the paper link; I hadn't seen that yet
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<ktemkin>
(also, I just saved it to my bookmark manager / reading list, which I haven't done for anything in a while, and is maybe some personal progress towards "having a genuine interest in anything tech, again" ^_^)
<ktemkin>
(or maybe it's the amphetamine, who knows)
<Gracana>
:X
<Gracana>
Recently I've been coping with that by realizing that I *will* circle back around to it, I just have to give my brain time with some other endeavor so it can reset and find novelty in the original thing again. If that makes sense.
<Gracana>
And it works, ish. Deadlines are rough.
<whitequark>
ktemkin: nice :3
<whitequark>
i'm in the "amphetamine works if nothing else does" camp, personally
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<awygle>
i wish i tolerated amphetamines better :(
<whitequark>
try phenidates
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<Gracana>
I have decided.... boo SMARC. I don't have enough serdes channels to do it justice. Which is fine. So today I picked out power supply components and started drawing out some stuff for a VGA interface using the analog devices adv7125 330MHz triple video DAC
<Gracana>
and I will continue with the original plan of "let's make something goofy and anachronistic"
<awygle>
i have approx the same reaction to those
<Gracana>
VGA, PS/2, big ol' parallel bus
<Gracana>
to which what with the who now?
<awygle>
sorry, that was @ wq, not you
<Gracana>
haha ok
<Gracana>
well, not funny in the original context but it makes more sense
<ktemkin>
awygle: out of curiosity, what amphetamine blend have you tried?
<awygle>
i have tried dextroamphetamine-amphetamine, methylphenidate, and the extended release versions of both of those
<awygle>
all of them made me feel like my head was in a vise ~12 hours after the first dose, it was very weird
<awygle>
lasted about 30m each time
<whitequark>
awygle: as in, strong headache?
<awygle>
strong headache with a distinctive squeezing feel. concentrated on the temples.
<whitequark>
huh, weird.
<whitequark>
and unfortunate
<awygle>
yep. maybe i'll try again someday. currently on an ssri which seems to be pretty ok
<ktemkin>
I think I'm more surprised at the timing of the presentation than in the headache itself
<whitequark>
i could speculate but all i know is that drugs affect people in most unexpected ways all the time
<ktemkin>
mm
<awygle>
the timing surprised the shit out of me too, isn't the half life supposed to be like five hours
<whitequark>
well yes
<whitequark>
that doesn't mean it stops working in five hours!
<whitequark>
it means you have 1/5 or so of the intial concentration
<ktemkin>
nor does it mean that your body reaches steady-state upon purging most of it
<whitequark>
yeah
<ktemkin>
there are alternate amphetamine formulations (like just the dextro-) that people sometimes find give them Different Degrees of side effects
<ktemkin>
if your doctor's willing to put up with you trying various things and you're willing to try experimenting to see all the different ways your head can feel awful
<whitequark>
there are also alternate phenidate structural isomers with similar qualities, but they're harder to obtain
<whitequark>
sadly i'm not aware of any way to resolve these issues other than "try and see"
<awygle>
i'll definitely keep in mind the alternative formulations
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