<awygle>
what do I do with electronics stuff that is useful, just not to me anymore, but too small to sell?
<cr1901_modern>
give it to me :)?
<awygle>
like, can I donate three TOSLINK fibres to the Salvation Army?
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<cr1901_modern>
ahhh, I don't think I can use those...
<awygle>
I somehow have a ton of audio cabling including a 15 foot 3.5mm extender cable
<awygle>
(which like, that's an analog cable, that must be terrible for signal quality...)
<whitequark>
awygle: hmmm you can probably use those
<whitequark>
TOSLINK xceivers are cheap and it's an easy way to do high-ish data rate optoisolated
<q3k>
whitequark: I think awygle is looking for ways to reduce his stash of junk, not find more excuses to keep it growing ^^
<awygle>
^ that
<awygle>
TOSLINK is cool and I might build it into a project but I don't want to just keep it because maybe someday
<q3k>
awygle: find local hackerspace. figure out what their policy is on hw donations. most likely they are willing to look through your crap and take anything that's intersting (if it's a mature hackerspace, except less than 1 in 20 items being interesting). chuck everything else out.
<awygle>
hm good idea, requires going to the city tho :-P yeah I'll do that
<awygle>
hackerspaces are depressingly thin on the ground in this area
<shapr>
I am unreasonably thrilled, probably because it took me ten hours of reading and trying things.
<shapr>
also, pmod headers on the beaglewire are upside down!
<q3k>
shapr: great job
<shapr>
w00!
* shapr
dances cheerfully
<fseidel>
new to FPGAs, or just verilog?
<fseidel>
also, good job!
<shapr>
fseidel: I've been reading about FPGAs for months, not sure if that counts as new or not
<shapr>
but yes, this is the first FPGA thing I've done
<fseidel>
cool, welcome to the fun club :-)
<shapr>
yay, thanks!
<azonenberg_work>
Fun Programmable Gate Array? :D
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<fseidel>
so I dunno if your dev board has some sort of video output, but back when I TAed an intro logic design course, one of the labs that students really loved was implementing pong on an FPGA
<fseidel>
it might be a fun one to try
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<cr1901_modern>
We didn't get to video output in our intro to logic design course ._.
<cr1901_modern>
I did a VGA driver as part of an "IP library" for Uni during the final semester, but I don't think video was on the table at all during Dig I
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<fseidel>
the first few labs are combinational, then you do a state machine for a coin acceptor
<fseidel>
and then pong or some other game depending on the semester
<fseidel>
sometimes we do breakout
<fseidel>
pong is definitely more beginner friendly though
<shapr>
I'm using a BeagleWire, it has pmod connectors
<cr1901_modern>
Our final project was a stopwatch
<fseidel>
the secret to VGA is it's just a few counters ;-)
<fseidel>
we usually offer a small number of bonus points for especially creative variants of the game. someone made the ball a tiny pixel-art of the prof's face :-)
<q3k>
pong via vga is a super cool fpga demo
<fseidel>
the reason I mention this is that it's challenging enough to learn something new and feel rewarding, while also being simple enough for someone relatively new to figure out
<q3k>
yep
<cr1901_modern>
I would say "VGA is a bit tough for a final project". Well it was tough for me doing it back then. I remember two issues: finding good front/back porch timing info, and trying/failing to synthesize a 25.125MHz clk before realizing 25MHz works
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<fseidel>
oh yeah, we just tell them to use the 50MHz clock on the board and toggle the line every other clock :-P
<fseidel>
VGA is extremely loose, which makes it beginner friendly
<azonenberg_work>
my one time playing with VGA and an LCD monitor (not a CRT)
<azonenberg_work>
i coudlnt get it to lock on even with constant color
<azonenberg_work>
the timing was off and without any way to know what was wrong i was lost
<whitequark>
i remember doing this is on an atmega
<whitequark>
this is when i discovered that an atmega can't interrupt an instruction
<fseidel>
CRT makes it easier because they're much more tolerant of out-of-spec signals
<whitequark>
so the timing is a bit off if you use jumps or loads
<fseidel>
were you trying to pull a linus akesson?
<azonenberg_work>
whitequark: i was using an xc9500 series part
<whitequark>
no i was bored and young
<azonenberg_work>
so it was cycle accurate timing
<azonenberg_work>
But i don't know what was wrong and i probably no longer have the RTL handy
<q3k>
it also theaches students to simulate first :)
<q3k>
because counting cycles on a scope is (well, was) pain
<fseidel>
yeah, this is when most students bust out the waveform viewer and make sure it actually works out
<whitequark>
oh i only had an С1-68 analog scope
<fseidel>
some don't then get "out of spec signal" on the monitor and beg us to fix it, which is when we tell them to open up the simulator and see why it's not working
<azonenberg_work>
Yeah i ran a simulation and couldn't figure out what was wrong
<azonenberg_work>
the timing looked right
<azonenberg_work>
Which probably meant, i was targeting the wrong timing :p
<q3k>
sometimes back/front porch is confusing
<q3k>
and people get that mixed up
<fseidel>
yeah, it's all relative to what you consider the front and back
<azonenberg_work>
i'd much prefer to do displayport if i was ever going to do video on one of my projects
<cr1901_modern>
unless that also includes displayport b/c Idk how the standards are related
<fseidel>
yeah, it's just differential pairs of RGB values clocked out bit by bit, right?
<q3k>
getting TMDS working is probably the toughest part
<cr1901_modern>
it's encoded according to a table
<fseidel>
is that the display identifier thing?
<q3k>
no, it's the 8/10b encoding for the data on the wire
<fseidel>
oh
<fseidel>
I think USB uses something similar, right?
<fseidel>
I seem to recall this from implementing a USB 2.0 host...
<whitequark>
lol no USB uses NRZI and bit stuffing
<whitequark>
which is a batshit insane variable length encoding
<fseidel>
oh right, it's been a while
<fseidel>
you have to stall the FSM when you find the stuffed bits
<fseidel>
it's... something
<azonenberg_work>
meanwhile displayport uses the standard ibm 8b10b code :D
<sorear>
cycle-deterministic response to interrupts seems…rare
<cr1901_modern>
you can get it on CMOS versions of 6502 :P
<fseidel>
shapr: anyway, I really hope we didn't scare you too much, but yeah, grab a pmod VGA and try video, it's super rewarding!
<sorear>
not if said 6502 is running random instructions
<fseidel>
yeah, 6502 only checks I flag during decode
<fseidel>
this is why C64 demos set up nop chains so that interrupt jitter is reduced to 2 cycles for timing critical effects
<cr1901_modern>
I meant the WAI insn
<fseidel>
oh
<sorear>
maybe you could set the timer for a few cycles before when you actually need to do work, then read the timer and do a fine delay in the handler
<fseidel>
that one's 65C02 only, right?
<cr1901_modern>
right
<fseidel>
that would explain why C64 demos don't just do that
<cr1901_modern>
you can set up an interrupt handler in a special way such that your interrupt latency is consistently 1 cycle
<q3k>
cr1901_modern: hm, they sometimes appearify in cheap batches on ebay
<q3k>
i don't wirewrap backplanes, just connect random equipment together, so I just use 2.5" headers (the cheaper/sharper the better)
<q3k>
toughest connections on those yellow pin headers that come with stm32 bluepills ^^
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<cr1901_modern>
IME wire wrap doesn't wrap around generic 2.5" headers well. Experience not typical of course
<q3k>
Hum.
<q3k>
never had an issue.
<cr1901_modern>
Not that I think wire wrap is _bad_. Just never worked for me :P
<q3k>
what was the problem?
<cr1901_modern>
The wire wouldn't fuse to the header pin
<q3k>
was it a square post header pin?
<cr1901_modern>
so it would instantly slide off if you touched it, moved it, breathed wrong
<q3k>
very odd
<cr1901_modern>
yes (and a couple of circular ones too :)...)
<q3k>
what wire are you using?
<cr1901_modern>
uhhh, give me a few mins and I'll get back to you :P?
<q3k>
'standard' 30 awg kynar?
<cr1901_modern>
That sounds right
<cr1901_modern>
it was either 28 or 30
<q3k>
i'm dumbfounded, I've used probably 4 different brands of 30awg kynar solid core wire, on pin headers of all sorts, never had anything just fall off
<cr1901_modern>
it
<cr1901_modern>
s 28 gauge
<cr1901_modern>
I'll check for 30 gauge in a bit
<q3k>
please film the wire wrapping and failure mode ^^
<cr1901_modern>
can it wait till tomorrow when I have natural light?
Guest84957 is now known as felix_
<q3k>
oh yeah, absolutely
<q3k>
just curious
<cr1901_modern>
Also notably... At the top of my tool, there's supposed to be a very small hole where the wire goes in
<cr1901_modern>
I can no longer see that hole... I wonder if it got clogged/I need a new tools
<shapr>
yes, if you don't put the wire into that hole, you don't get the massive PSI needed to cold weld the wire onto the square pin
<shapr>
mind you, wire wrap is pretty much a dead technology at this point...
<shapr>
but if we ever have an in-person meeting of the denizens of this irc channel, I will bring my wire wrap supplies
<q3k>
35C3 OpenFPGA and Wire Wrapping assembly
<shapr>
oh yeah!
<cr1901_modern>
I somehow doubt I'll be able to travel to that, but I appreciate the sentiment :)
<shapr>
so we need a north america OpenFPGA meetup?
<cr1901_modern>
Yes, preferably in Philadelphia or DC :P
<shapr>
hm, I can do that
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<sorear>
there's also some kind of regular pnw openfpga meetup
* sorear
thought cr1901_modern was NJ
<cr1901_modern>
sorear: I am
<cr1901_modern>
South Jersey tho lol
<cr1901_modern>
Both Philly and DC are trivial to get to by train
<cr1901_modern>
or $whatever_transportation_mode_you_prefer
<cr1901_modern>
I just don't like using my car 'cept for local stuff
<sorear>
*is still pretty new to the area, finds a map*
<fseidel>
I met rqou IRL a few times, does that count?
<cr1901_modern>
Ashland allows me to avoid basically every major highway into Philly
<cr1901_modern>
Which is horrific to get in and out of during any given weekday
<sorear>
is there like, a good reason there's only one line leaving philly east
<cr1901_modern>
Only room for one track over Ben Franklin Bridge :P?
<cr1901_modern>
In any case, get off PATCO at 8th and Market, take a SEPTA subway directly to 30th street. Catch an Amtrak to wherever you want.
<cr1901_modern>
and that's my foolproof* way to avoid Philly traffic :)
<cr1901_modern>
(*Not comprehensively tested)
<awygle>
yessss I have reached a milestone and vacuumed the new apartment
<sorear>
surprised there isn't more of MIT-area presence here, anyway
<cr1901_modern>
awygle: Yay
<cr1901_modern>
fseidel: Sure :P
<cr1901_modern>
sorear: MIT-area presence?
<sorear>
people who live near MIT and work on ##openfpga stuff
<cr1901_modern>
ahhh
<cr1901_modern>
sorear: Also, re: one line leaving philly east... I don't know the details, but there are tunnels underneath the Ben Franklin Bridge. They were meant for a trolley line if memory serves, but never came to fruition
<fseidel>
I'm in the MIT area, that's home for me
<cr1901_modern>
sorear: You're from Boston? Or are you new to _that_ area?
<fseidel>
nah, I've been here my whole life
<fseidel>
spent summer interning in CA, and I go to school in Pittsburgh
<sorear>
cr1901_modern: I'm from San Diego, I'm relocating to new england
<cr1901_modern>
ahhh
<fseidel>
it's a great place, enjoy your time here!
<cr1901_modern>
Also, that map I linked is idiotic
<fseidel>
try the chowder :-)
<cr1901_modern>
Why would I get off PATCO to get on a bus to go over the bridge?
<cr1901_modern>
When PATCO goes over the bridge by itself?
<sorear>
because Google Maps routes you from a point to a point, not a city to a city
<sorear>
it has decided that "Philadelphia" means City Hall, which is a long walk from the end of PATCO, so there's a transfer
<cr1901_modern>
Hmmm
<cr1901_modern>
I see... walking a few blocks isn't an issue for me, but it could be for others
<cr1901_modern>
(using the silly City Hall example)
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<rqou>
azonenberg_work: ping?
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<rqou>
ok, since shapr asked me to explain what is going on with the xilinx effort, i will state my version of events here in public for the record
<rqou>
my version of events begins some time in fall 2017
<rqou>
clifford starts posting teasers of project xray
<rqou>
when clifford visited various universities and companies here in the bay area some time in the fall of 2017, i asked him about this and the only thing he would answer was "i can't talk about it"
<rqou>
since i was busy with grad school i didn't push further
<rqou>
however, eventually later i would learn that many people (e.g. azonenberg_work, felix_) had privileged access to it
<rqou>
anyways, fast forward to ccc in december 2017
<rqou>
m!thro finally tells me the reason for this first embargo
<rqou>
supposedly it was related to legal concerns with the $SPONSOR funding the effort
<rqou>
i have promised not to reveal the $SPONSOR, but i suggest investigating the employment history of the people who worked on it
<rqou>
anyways, m!thro tells me about the vpr ice40 effort and asks me to contribute
<rqou>
i try to contribute but ended up too burned out by grad school to actually do much
<rqou>
i was especially unhappy that this project was not open development (i.e. communication channels) even though it was open source
<rqou>
anyways, eventually as the jan-may 2018 semester progresses i slowly start to hear about other secret projects happening (nextpnr)
<rqou>
towards the end around april i was unhappy enough with the fact that *) no MVP had been demonstrated *) the projects weren't open development that i decided to hack on my own implementation
<rqou>
it makes enough progress that i could see how to get to MVP but i didn't have time to finish it so i shelved it
<rqou>
at the end of may i visit azonenberg_work who seemed to have a lot of privileged access to information
<rqou>
he suggests that i work on a new RE effort instead
<rqou>
so i started project chibi
<rqou>
at this point i knew for sure that nextpnr was secretly happening in the background
<rqou>
and so since i was extremely unhappy with the lack of transparency i made sure that project chibi was done as fast as possible and as open as possible
<rqou>
around this time i also managed to speak to m!thro IRL and ask him why there was so much lack of transparency going on
<rqou>
this was at the post maker faire dinner
<rqou>
the understanding i got from that conversation was that "the team" was trying to carefully orchestrate their releases to get maximum "impact"
<rqou>
and the between-the-lines subtext that i got from the conversation was that part of this involved keeping up the "status" of the core devs
<rqou>
this was a big reason why project chibi was done as fast as possible -- to send a message that "the team" is not as critical as this messaging might want
<rqou>
anyways, i finish project chibi and release it
<rqou>
i then managed to ask d!gshadow why nextpnr was secret and i got a different answer
<rqou>
namely to preserve the working relationship with the vpr developers
<rqou>
this seemed questionable to me, but i accepted that
<rqou>
around this point in time clifford and edmund visited the bay area again
<rqou>
i spoke to them and got completely stonewalled with no real answers at all
<rqou>
however i did observed them leaking more information to t!nyfpga
<rqou>
so it seemed that "everybody else" was somehow getting their hands on more information
<rqou>
anyways, at this point in time i had a reverse-engineered bitstream but no tool to plug it into, and i knew of several embargoed/otherwise-not-transparent projects going on
<rqou>
so i purposely did my vpr hack as quickly as possible to reach MVP as soon as possible
<rqou>
this was specifically done to send the message "you are not as critical as you like to present yourselves. it is quite possible to replace you if you keep playing games"
<rqou>
but it was also specifically done to not upset the vpr devs
<rqou>
anyways, after releasing this, i eventually discover that d!gshadow had banned me from siliconpr0n in retaliation
<rqou>
i also discover at this point that even _more_ people (whitequark) were getting privileged access to nextpnr
<rqou>
so i finally publicly announce that i believe "the team" is acting in bad faith
<rqou>
and then q3k and daveshah contacted me and finally started giving me a different story as to what had happened
<shapr>
yikes, drama
<rqou>
note that timeline-wise this is the first time in _close to a year_ that anyone even had the pretense of being open or transparent rather than just stonewalling me
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<rqou>
anyways, q3k and daveshah tell me that nobody employed by symbioticeda was happy
<rqou>
they also told me that "the team" as i had understood it was not a single unit
<rqou>
apparently symbioticeda had done their nextpnr effort independently of any $SPONSOR-funded efforts
<rqou>
i did get one more piece of information that i've been asked not to share
<rqou>
but neither q3k nor daveshah were willing to give me the one final piece of information regarding the relationship between symbioticeda and $SPONSOR
<rqou>
as in, both have explicitly refused to give me the _same_ piece of information
<rqou>
so at this point in time i stand by my assessment that the $SPONSOR-funded members of the team are acting outright maliciously
<rqou>
symbioticeda does not seem to be acting maliciously but their motives are questionable at best
<rqou>
hence my starting on kinglerpar and my recommendation to not work with either of these teams
<rqou>
fin
* shapr
gets off the roller coaster, dizzy but enlightened
<prpplague>
digshadow: i had hoped they had some of the AMD bit-slice stuff
<kc8apf>
more a gaffe that I started something new instead of working with one of the existing code bases
<prpplague>
hey, sometimes you gotta reinvent the wheel
<shapr>
haha
* cr1901_modern
also has a few chips he wishes the archive had
<prpplague>
i've been wanting to send off a UC-2000 main board to get it decap'd and photographed, just can't ever find the time
<kc8apf>
especially when you want a kevlar-belted radial when the focus has been on improved stone chiseling technique
<shapr>
I have some zero-defect cell broadband engine chips around here in a box
<rqou>
based on the behavior i just described i wouldn't
* shapr
hugs rqou
<rqou>
unfortunately the people involved are really good at both social media and "cookie licking"
<shapr>
huh, new term for me
<kc8apf>
rqou: I expect that will change
<awygle>
an evocative term to be sure, I also had not heard it in this context
<cr1901_modern>
I misread as cookie clicking... like the game
<noopwafel>
one more reason I love people 'duplicating work', it's not only (a) awesome and (b) learning experience in any case, but also (c) more likely something gets done :)
<kc8apf>
I'm getting more positive feedback on writing up blog posts about how everything works than on the actual code I'm writing
<cr1901_modern>
It's also fragmentation, so I'm not certain I agree with (c) due to "time lost duplicating" (something something Jeff Atwood says "never do a rewrite" something)
* cr1901_modern
holds the above opinion semi-loosely
<kc8apf>
fragmentation is only bad if there is never a reconciliation
<kc8apf>
trying new ideas is good
<kc8apf>
never coalescing when one idea prevails is bad
<cr1901_modern>
That's a reasonable stance that I may steal for my own in the future :)
<awygle>
this is why i advocate so hard for interoperability
<shapr>
kc8apf: where's your blog again?
<kc8apf>
kc8apf.net
<awygle>
i do find a lot of things around Project X-Ray and the development of nextpnr... fishy, for lack of a better term
<awygle>
but if they come up with a framework i can plug cool PAR algorithms into, i don't really care that much
<awygle>
especially since it's MIT licensed (afaicfo)
<awygle>
i haven't yet looked to see whether or not they have though
* kc8apf
needs to look at nextpnr more closely
<awygle>
same
<kc8apf>
7-series is a beast to model correctly
<awygle>
anyway, if sketchy behavior continues, MIT license means i can just not contribute any cool shit i do upstream if it gets bad enough :/
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* cr1901_modern
has no comment
<awygle>
cr1901_modern is wise
* awygle
goes back to work
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<Prf_Jakob>
So newbie question, I'm desiging a two layer board to level shift a mc68k cpu socket to 3v.I can route out all of the signals on one layer. The only problem is +5V. I'm thinking of running that on the back of the board. But that will mean crossing a couple of the front side traces. How much interferance would that produce?
<fseidel>
wait, are we seriously both working on M68K boards? what are the odds? :-P
<fseidel>
that doesn't seem to bad given that it's just a DC power trace
<fseidel>
*too
<Prf_Jakob>
Ah okay
<Prf_Jakob>
fseidel: Hehe, small world. You wanted to plg a 030 into a 000 socket right?
<fseidel>
I'd go for a second opinion, but I don't see anything wrong with that
<fseidel>
yeah
<fseidel>
plus some SRAM for a scratchpad
<Prf_Jakob>
Ah cool, I want to do a FPGA mc68k core. Not having high hopes of finishing it, but at least I can learn some EE on the way.
<cr1901_modern>
(I didn't actually understand the tweet, I just like Star Cruiser)
<fseidel>
never played it, I love the OST though, incredible music
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<fseidel>
actually, that's not strictly true, I played about 10 minutes of the fan translation of the MD verion
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<awygle>
cr1901_modern: yes, but crossing the traces makes it worse (under some assumptions) because they break up the return path and the current has to detour around the traces
<cr1901_modern>
awygle: Oh, I just call that "impedance mismatch" and handwave it :)
<awygle>
yeah it can be understood in many ways at many levels of detail :-)
<awygle>
lots of things are like that, I realized recently how many things are particle filters
* awygle
has a vision of "simulate serdes through castellated holes" on his projects list
<awygle>
i badly want an ECP5/Cyclone 10 GX "module" that i can slap down for high-speed SERDES on cheap boards
<awygle>
make the "real pcb process" stuff as small as possible to save $$$
<awygle>
but connectors are also $$$ as well as big. so... castellations. if they're not too bad for SI.
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<Prf_Jakob>
awygle: SODIMM connecter is only $
<awygle>
Prf_Jakob: true, and ENIG moooooostly works for that purpose :p. SODIMM or mPCI/m.2 are my backup plans.
<awygle>
something like the PicoEVB but for my preferred FPGAs
<Prf_Jakob>
awygle: I need 60+ I/O so PicoEVB is ait lacking.
<Prf_Jakob>
ait = a bit.
<awygle>
for sure
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<azonenberg_work>
awygle: y u no qstrip?
<azonenberg_work>
is that such a big deal compared to the cost of a nice pcb and serdes-capable fpga?
<gruetzkopf>
4-layer has gotten so cheap
<azonenberg_work>
Yeah it is
<azonenberg_work>
But I need 6L for some of my pending projects
<gruetzkopf>
i remember when 2l prototype was as expensive as 6l is today
<azonenberg_work>
yeah back in the day i used to DIY etch my own boards
<azonenberg_work>
now its just not worth it
<awygle>
4l ecp5 is like 20$ total. Q strip adds almost 50% considering only the *module*
<azonenberg_work>
ah ok, the module i am looking at doing w/ stm32 + artix will be substantially more
<azonenberg_work>
But i'm talking about adding hyperram, ethernet, etc
<azonenberg_work>
(And no serdes)
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<Prf_Jakob>
azonenberg_work: Are you going to use the fpga as bridge between the smt32 and hyperram? Like a northbridge?
<awygle>
Admittedly for a cyclone design q strip starts making sense
<awygle>
But at that point the castellation process might be proven (or disproven) by the ecp design
<azonenberg_work>
Prf_Jakob: not exactly
<azonenberg_work>
I mean, i could
<azonenberg_work>
The fpga and stm32 are connected by the camera interface (fpga->mcu) as well as 100M ethernet (bidirecitonal)
<azonenberg_work>
The primary intended use case is for the FPGA to do protocol offload and datapath processing for incoming ethernet data and then have some contrl plane stuff on the MCU
<azonenberg_work>
Also, they can be used independently
<Prf_Jakob>
Oh cool
<azonenberg_work>
in my switch project for example the artix on the module will be an io expander for the big kintex on the host board
<azonenberg_work>
While the stm32 will run the management cli
<Prf_Jakob>
Very cool :D
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