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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPyop
<openfpga-github> openfpga/master f3ead16 Andrew Zonenberg: gp4par: Removed spurious "net has no load" warnings for infrred GP_ACMP blocks. Fixes #42.
<azonenberg> also woo that was 888 commits this year, lol
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<openfpga-github> [yosys] azonenberg pushed 6 new commits to master: https://git.io/vPyXc
<openfpga-github> yosys/master 15fb566 Clifford Wolf: Bugfix in "miter -assert" handling of assumptions
<openfpga-github> yosys/master 0bcc617 Clifford Wolf: Added "yosys-smtbmc --cex <filename>"
<openfpga-github> yosys/master 6425d34 Clifford Wolf: Added clk2fflogic support for $dffsr and $dlatch
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vPyXz
<openfpga-github> yosys/master a818472 Andrew Zonenberg: greenpak4: added model for GP_EDGEDET block
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vPy1a
<openfpga-github> yosys/master 091d32b Andrew Zonenberg: Added GLITCH_FILTER parameter to GP_DELAY
<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vPy1S
<openfpga-github> openfpga/master 67c4441 Andrew Zonenberg: greenpak4: Added GP_EDGEDET core
<openfpga-github> openfpga/master 822548d Andrew Zonenberg: tests: initial implementation of Ethernet test
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<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vPyyO
<openfpga-github> yosys/master e78fa15 Andrew Zonenberg: greenpak4: Added GP_PGEN cell definition
<openfpga-github> [yosys] azonenberg pushed 1 new commit to master: https://git.io/vPyy0
<openfpga-github> yosys/master 1cca156 Andrew Zonenberg: Fixed typo in last commit
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPy9K
<openfpga-github> openfpga/master 835caa9 Andrew Zonenberg: greenpak4/gp4par: Implemented GP_PGEN block. Fixes #33.
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<azonenberg> The lack of clock enables in greenpak is a bit annoying
<azonenberg> i think i am going to have to write some really weird RTL to avoid needing muxes everywhere
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<azonenberg> This ethernet project is proving to be exactly what i needed, lol
<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vPy7E
<openfpga-github> openfpga/master 3023910 Andrew Zonenberg: tests: Lots more work on Ethernet test
<openfpga-github> openfpga/master 1207e91 Andrew Zonenberg: gp4par: Removed stale debug print
<azonenberg> a) an excuse to implement most of the remaining digital hard IP
<azonenberg> b) a test case for the same
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<openfpga-github> [openfpga] azonenberg pushed 2 new commits to master: https://git.io/vPyNh
<openfpga-github> openfpga/master c9f03cd Andrew Zonenberg: greenpak4: Continue work on Ethernet test
<openfpga-github> openfpga/master f60bb27 Andrew Zonenberg: greenpak4: Minor tweaks to improve routability of dense designs using multiple LUT4s
<azonenberg> Wow, lol
<azonenberg> I'm using 80% of the cross connections
<azonenberg> but only 30% of the counters, 83% of the FFs, 34% of the LUTs
<azonenberg> Down to 65% x-conns after removing some of the debug outputs
<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPyAn
<openfpga-github> openfpga/master 2c1d89c Andrew Zonenberg: tests: Removed some debug outputs on Ethernet test
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<cr1901_modern> https://github.com/azonenberg/openfpga/blob/master/tests/greenpak4/Ethernet.v Wow... WTAF?! An Ethernet PHY on a GP4?
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<azonenberg> Not a whole PHY, at least for now
<azonenberg> i'm going to be hard pressed enough just doing 10baseT autonegotiation
<azonenberg> ignoring incoming packets
<azonenberg> and not sending anything
<azonenberg> just getting to the point that the other end detects a link
<azonenberg> is my current goal
<azonenberg> But we'll see how far i can take it
<azonenberg> the chip is far from full
<azonenberg> and if i improve some hard IP support i'll be able to reduce utilization further
<azonenberg> But the WTF factor was intentional
<azonenberg> I wanted something to show off how far the tools have come
<cr1901_modern> Well, you succeeded. I'm full of WTFs right now.
<rqou> i'm quite surprised it's possible
<azonenberg> Also to be clear i'm not linking up yet
<azonenberg> there's a bug somewhere
<azonenberg> i definitely have enough gates to do it
<cr1901_modern> I have so many WTFs to give that I don't know what to do with them
<rqou> my initial impression of greenpak was "too few state bits"
<azonenberg> i just plugged it into my cisco and i'm seeing FLPs in both directions
<azonenberg> somewhere, something isnt lining up
<azonenberg> i'm trying to decode the LA'd FLP signal it sent me now
<azonenberg> to figure out if it's sending an error code
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPSvq
<openfpga-github> openfpga/master 1acdf7f Andrew Zonenberg: tests: Continued work on Ethernet test
<azonenberg> so it looks like i need to stop sending FLPs
<azonenberg> and instead send single link integrity pulses
<azonenberg> once the link is considered to be up
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<azonenberg> yep thats it
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPSvA
<openfpga-github> openfpga/master 793b6a4 Andrew Zonenberg: greenpak4: Ethernet test now correctly generates link-up blindly (assuming correct aneg on far end)
<azonenberg> keccak#
<azonenberg> *Mar 5 17:19:22: %LINEPROTO-5-UPDOWN: Line protocol on Interface GigabitEthernet0/22, changed state to up
<azonenberg> *Mar 5 17:19:21: %LINK-3-UPDOWN: Interface GigabitEthernet0/22, changed state to up
<azonenberg> :D
<azonenberg> Ethernet in 12 LUTs, lol
<rqou> now test it with a realtek on the other end :P (i've hit autoneg bugs on realtek before years ago, and apparently my father hit autoneg bugs on realtek some more years ago)
<azonenberg> Not tonight
<azonenberg> its already waaay past bedtime
<azonenberg> i have to get up for work in a bit over six hours :p
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<openfpga-github> [openfpga] azonenberg pushed 1 new commit to master: https://git.io/vPSJ8
<openfpga-github> openfpga/master a7e7e46 Andrew Zonenberg: tests: removed unnecessary debug output
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<openfpga-github> [yosys] azonenberg pushed 3 new commits to master: https://git.io/vPSdB
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<openfpga-github> yosys/master 0b3885b Clifford Wolf: Merge pull request #250 from azonenberg/master...
<openfpga-github> yosys/master 3655d7f Clifford Wolf: Added "setparam -type"
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