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openfpga-github >
openfpga/master f3ead16 Andrew Zonenberg: gp4par: Removed spurious "net has no load" warnings for infrred GP_ACMP blocks. Fixes #42.
01:33
<
azonenberg >
also woo that was 888 commits this year, lol
01:35
<
openfpga-github >
openfpga/gh-pages 7216609 Travis CI User: Update documentation
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openfpga-github >
yosys/master 15fb566 Clifford Wolf: Bugfix in "miter -assert" handling of assumptions
02:29
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openfpga-github >
yosys/master 0bcc617 Clifford Wolf: Added "yosys-smtbmc --cex <filename>"
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openfpga-github >
yosys/master 6425d34 Clifford Wolf: Added clk2fflogic support for $dffsr and $dlatch
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openfpga-github >
yosys/master a818472 Andrew Zonenberg: greenpak4: added model for GP_EDGEDET block
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openfpga-github >
yosys/master 091d32b Andrew Zonenberg: Added GLITCH_FILTER parameter to GP_DELAY
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openfpga-github >
openfpga/master 67c4441 Andrew Zonenberg: greenpak4: Added GP_EDGEDET core
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openfpga-github >
openfpga/master 822548d Andrew Zonenberg: tests: initial implementation of Ethernet test
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<
openfpga-github >
openfpga/gh-pages 03e8013 Travis CI User: Update documentation
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travis-ci >
azonenberg/openfpga#121 (master - 67c4441 : Andrew Zonenberg): The build passed.
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openfpga-github >
yosys/master e78fa15 Andrew Zonenberg: greenpak4: Added GP_PGEN cell definition
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<
openfpga-github >
yosys/master 1cca156 Andrew Zonenberg: Fixed typo in last commit
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openfpga-github >
openfpga/master 835caa9 Andrew Zonenberg: greenpak4/gp4par: Implemented GP_PGEN block. Fixes #33.
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openfpga-github >
openfpga/gh-pages 164d64b Travis CI User: Update documentation
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<
travis-ci >
azonenberg/openfpga#122 (master - 835caa9 : Andrew Zonenberg): The build passed.
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04:57
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azonenberg >
The lack of clock enables in greenpak is a bit annoying
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<
azonenberg >
i think i am going to have to write some really weird RTL to avoid needing muxes everywhere
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azonenberg >
This ethernet project is proving to be exactly what i needed, lol
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openfpga-github >
openfpga/master 3023910 Andrew Zonenberg: tests: Lots more work on Ethernet test
05:19
<
openfpga-github >
openfpga/master 1207e91 Andrew Zonenberg: gp4par: Removed stale debug print
05:19
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azonenberg >
a) an excuse to implement most of the remaining digital hard IP
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azonenberg >
b) a test case for the same
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<
openfpga-github >
openfpga/gh-pages 36d8f09 Travis CI User: Update documentation
05:26
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travis-ci >
azonenberg/openfpga#123 (master - 3023910 : Andrew Zonenberg): The build passed.
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openfpga-github >
openfpga/master c9f03cd Andrew Zonenberg: greenpak4: Continue work on Ethernet test
05:59
<
openfpga-github >
openfpga/master f60bb27 Andrew Zonenberg: greenpak4: Minor tweaks to improve routability of dense designs using multiple LUT4s
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azonenberg >
Wow, lol
06:00
<
azonenberg >
I'm using 80% of the cross connections
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azonenberg >
but only 30% of the counters, 83% of the FFs, 34% of the LUTs
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azonenberg >
Down to 65% x-conns after removing some of the debug outputs
06:03
<
openfpga-github >
openfpga/master 2c1d89c Andrew Zonenberg: tests: Removed some debug outputs on Ethernet test
06:05
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travis-ci >
azonenberg/openfpga#124 (master - c9f03cd : Andrew Zonenberg): The build passed.
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<
openfpga-github >
openfpga/gh-pages d41661c Travis CI User: Update documentation
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<
travis-ci >
azonenberg/openfpga#125 (master - 2c1d89c : Andrew Zonenberg): The build passed.
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azonenberg >
Not a whole PHY, at least for now
06:49
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azonenberg >
i'm going to be hard pressed enough just doing 10baseT autonegotiation
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<
azonenberg >
ignoring incoming packets
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<
azonenberg >
and not sending anything
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azonenberg >
just getting to the point that the other end detects a link
06:49
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azonenberg >
is my current goal
06:49
<
azonenberg >
But we'll see how far i can take it
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azonenberg >
the chip is far from full
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azonenberg >
and if i improve some hard IP support i'll be able to reduce utilization further
06:50
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azonenberg >
But the WTF factor was intentional
06:50
<
azonenberg >
I wanted something to show off how far the tools have come
06:51
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cr1901_modern >
Well, you succeeded. I'm full of WTFs right now.
06:53
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rqou >
i'm quite surprised it's possible
06:53
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azonenberg >
Also to be clear i'm not linking up yet
06:53
<
azonenberg >
there's a bug somewhere
06:53
<
azonenberg >
i definitely have enough gates to do it
06:53
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cr1901_modern >
I have so many WTFs to give that I don't know what to do with them
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rqou >
my initial impression of greenpak was "too few state bits"
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azonenberg >
i just plugged it into my cisco and i'm seeing FLPs in both directions
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azonenberg >
somewhere, something isnt lining up
06:53
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azonenberg >
i'm trying to decode the LA'd FLP signal it sent me now
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azonenberg >
to figure out if it's sending an error code
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openfpga-github >
openfpga/master 1acdf7f Andrew Zonenberg: tests: Continued work on Ethernet test
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azonenberg >
so it looks like i need to stop sending FLPs
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azonenberg >
and instead send single link integrity pulses
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azonenberg >
once the link is considered to be up
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<
azonenberg >
yep thats it
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openfpga-github >
openfpga/gh-pages a7de5b3 Travis CI User: Update documentation
07:30
<
travis-ci >
azonenberg/openfpga#126 (master - 1acdf7f : Andrew Zonenberg): The build passed.
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openfpga-github >
openfpga/master 793b6a4 Andrew Zonenberg: greenpak4: Ethernet test now correctly generates link-up blindly (assuming correct aneg on far end)
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<
azonenberg >
keccak#
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<
azonenberg >
*Mar 5 17:19:22: %LINEPROTO-5-UPDOWN: Line protocol on Interface GigabitEthernet0/22, changed state to up
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<
azonenberg >
*Mar 5 17:19:21: %LINK-3-UPDOWN: Interface GigabitEthernet0/22, changed state to up
07:36
<
azonenberg >
Ethernet in 12 LUTs, lol
07:36
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rqou >
now test it with a realtek on the other end :P (i've hit autoneg bugs on realtek before years ago, and apparently my father hit autoneg bugs on realtek some more years ago)
07:36
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azonenberg >
Not tonight
07:36
<
azonenberg >
its already waaay past bedtime
07:36
<
azonenberg >
i have to get up for work in a bit over six hours :p
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openfpga-github >
openfpga/gh-pages d650067 Travis CI User: Update documentation
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travis-ci >
azonenberg/openfpga#127 (master - 793b6a4 : Andrew Zonenberg): The build passed.
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openfpga-github >
openfpga/master a7e7e46 Andrew Zonenberg: tests: removed unnecessary debug output
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openfpga-github >
openfpga/gh-pages 0127be8 Travis CI User: Update documentation
08:01
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travis-ci >
azonenberg/openfpga#128 (master - a7e7e46 : Andrew Zonenberg): The build passed.
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openfpga-github >
yosys/master 042b67f Clifford Wolf: No limit for length of lines in BLIF front-end
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openfpga-github >
yosys/master 0b3885b Clifford Wolf: Merge pull request #250 from azonenberg/master...
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openfpga-github >
yosys/master 3655d7f Clifford Wolf: Added "setparam -type"
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