clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<perryprog> Hi. I know this is a potentially bad question, but I would like to visualize my verilog code as logic gates only. I'm wondering what the best way to do this is. Is something like https://github.com/nturley/netlistsvg the best way to go, or is there a nicer way?
<tpb> Title: GitHub - nturley/netlistsvg: draws an SVG schematic from a JSON netlist (at github.com)
<perryprog> i.e. when I currently do something like load...; synth; show I get a somewhat messy visualization with a lot of extra clutter. I would like to see the raw sequential logic with a more "standard" schematic for lack of a better word. Or even better, the ability to open up the circuit in Kicad to mess around with it futher.
<ZirconiumX> perryprog: I think pepijndevos_ got an importer to work for Yosys to KiCad
<ZirconiumX> perryprog: fundamentally though, Yosys doesn't work like a normal schematic
<perryprog> Hm, that's what I expected. It would be very cool to go from HDL to gate logic in a nice manner. Thanks for the help!
<ZirconiumX> Hah, you're talking to the person who *literally did just that*
<tpb> Title: VHDL to PCB - Wishful Coding (at pepijndevos.nl)
<ZirconiumX> perryprog ^
<perryprog> Hah. I'll give that a read.
<ZirconiumX> It's not bad, but it's nowhere near the efficiency of manual design. Currently.
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