clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tpb> Title: asynchronous reset mechanism of D flip-flop in yosys - Page 1 (at www.eevblog.com)
<promach> I am not sure that yosys-smtbmc tool is giving the right formal verification results
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<emeb_mac> on a lark, building icestorm/yosys/nextpnr on an RPi 4
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<futarisIRCcloud> emeb_mac: Should work fine. I've built it on an android termux.
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<emeb_mac> futarisIRCcloud: seems to be working so far. Slow, but no big issues yet (about 1/2-way thru yosys now)
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<emeb_mac> well, icestorm and yosys build OK, but nextpnr fails
<emeb_mac> nextpnr/3rdparty/qtimgui/ImGuiRenderer.h:57:5: error: ‘QOpenGLFunctions_3_2_Core’ does not name a type; did you mean ‘QOpenGLFunctionsPrivate’?
<emeb_mac> is it possible to configure the nextpnr build to leave out the GUI stuff? probably not needed on a headless system.
<emeb_mac> try cmake w/ -DBUILD_GUI=OFF I guess
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<Xark> emeb_mac: I tried this recently (on a 3...) and got past here, but was blocked by a problem with mutexes at run-time IIRC.
<emeb_mac> Xark: nextpnr built w/ GUI disabled. trying out tools now
<emeb_mac> yosys-abc has been spinning on a simple design for the last 10min w/o finishing.
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<Xark> emeb_mac: Hopefully it works. My Pi4 should arrived soon (I for sure needed fans and swap on the Pi3...took a while too). :)
<Xark> emeb_mac: I did get it working for regular ice40-8K (with archnepnr vs nextpnr).
<Xark> emeb_mac: I think I tried maybe a month or more ago (so ancient history). :)
<emeb_mac> Xark: this is my HX8K-based icestick 6502 design. It builds in a few sec on my i3 system. been running for the last 15 min or so and seems stuck at ABC: + mfs2 step
<emeb_mac> this is a 2GB RAM version of Pi4 and top reports that it's only using 0.7% of memory.
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<Xark> emeb_mac: Yeah, IIRC my memory issues were compiling (1GB and I think I had a browser window open). I think I used -j2 (-j4 was a bad idea I found).
<emeb_mac> yeah - I never use -j on systems with small memory. straight make w/o -j works fine (if slowly)
<Xark> emeb_mac: I also compiled RISC-V toolchain (overnight)...
<Xark> emeb_mac: But all those bars in htop looked so empty... :)
<emeb_mac> haha
<emeb_mac> well, I gave up and aborted. yosys-abc had been running on this for ~30min w/o evidence of progress. I suspect something wrong somewhere.
<emeb_mac> now trying with a different design. it also seems hung in yosys-abc
<Xark> emeb_mac: Was it using CPU (or wedged on mutex)?
<emeb_mac> It's using 100% of one CPU
<emeb_mac> and a tiny amount of RAM (0.6% in the current case)
<Xark> emeb_mac: I see. Kind of a bummer.
<Xark> emeb_mac: Presumably Pi related?
<emeb_mac> Xark: when you build these 6502 designs do you ever see this? "ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep")."
<emeb_mac> I've seen that before while building on PC but it doesn't seem to hurt anything
<Xark> emeb_mac: Hmm, a lot of spam, but I don't recall seeing that...
* Xark greps
<emeb_mac> I see it on PC for sure but the design builds fine
<Xark> emeb_mac: Yeah, it is there.
<emeb_mac> and PC blows right past the yosys-abc stuff that hangs on the Pi.
<Xark> emeb_mac: Like I mentioned, I have gotten some designs to build and run on the Pi (but not with arachne-pnr). I believe I got the RiscRV32 "PicoSoC" build and running (hence the RISC-V toolchain build I mentioned).
<Xark> Er, PicoRV32 :)
* Xark also remembers a lot of pauses on the Pi that were not noticeable on his PC. :)
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<pepijndevos_> Is there a way to control fan-out in abc? It seems to want to insert buffer chips above a certain threshold.
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<ZirconiumX> pepijndevos_: Have you made any optimisation to placement, or are you just dropping them in a grid as you go?
<pepijndevos_> ZirconiumX, it's just droppign them in a grid. There is no placement info in the netlist at all. I think Kicad ist just doing this.
<ZirconiumX> Ouch
<pepijndevos_> Which wont stop me from running the autorouter on it and watching it burn
<pepijndevos_> Skidl is *really* slow btw, the picorv32 has not yet completed generating the netlist. the 6502 took a looong time as well.
<pepijndevos_> I think we could look into graywolf and qrouter if we want to do bigger things than you can place by hand in Kicad.
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<cr1901_modern> https://github.com/YosysHQ/yosys/commit/e2fb8ebe86f49523168c413c734ce4690d740351#diff-04c6e90faac2675aa89e2176d2eec7d8L266 I never understood what this line meant in the README and now it's gone. What does/did it mean for yosys to synthesize "latched logic as feedback loops"?
<tpb> Title: Update README · YosysHQ/yosys@e2fb8eb · GitHub (at github.com)
<sorear> have you ever seen two back to back NOR gates in a book?
<cr1901_modern> yes I know what a latch looks like
<cr1901_modern> I guess my question is... "in the past did yosys emulate latches using a mux that fed back the output to input with one clock cycle delay?"
<sorear> Not a “clock cycle” delay - a combinatorial loop
<cr1901_modern> I don't see how that's "emulating" a latch then. The whole point of a latch is that the output gets fed back to the input.
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