clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<ZirconiumX> Is there any way of redirecting output of a single Yosys command in a script to a file?
<ZirconiumX> For example, printing `stat` to a file
<daveshah> ZirconiumX: Yes there is `tee -o`
<ZirconiumX> Thank you!
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<ZipCPU> Oh wow, thanks daveshah! I wasn't aware of that. That will be quite useful to me as I measure component usage!
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<ZirconiumX> If I wanted to collect stats on which gates are connected to each other, how would I go about that?
<daveshah> ZirconiumX: there is the edgetypes command but I don't think it tells you how many times each connection type appears
<ZirconiumX> edgetypes seems confusing to use
<ZirconiumX> daveshah: If I get Yosys to hit a log_abort(), should that be reported as a bug?
<daveshah> Yes
<ZirconiumX> Even if I'm doing dumb things?
<daveshah> I'd say so, unless you're messing with the code or something
<ZirconiumX> I'm not, so I'll report it
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<tpb> Title: ERROR: Abort in passes/techmap/extract_fa.cc:218 · Issue #1099 · YosysHQ/yosys · GitHub (at github.com)
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<ZirconiumX> daveshah: I want to say thank you for being so friendly and welcoming to me being an idiot.
<daveshah> Heh, no problem, it's always nice to see interesting uses of Yosys
<ZirconiumX> I think this is less of a use and more of an abuse
<ZirconiumX> Something which is curious to me is that abc doesn't seem to know how to use a mux8 (lut3?)
<daveshah> Yes, that is a known issue iirc
<daveshah> I don't think anyone knows why
<daveshah> btw, ad full adders - probably be better doing what the FPGA flows do; which is `synth -run :fine; techmap -map +/techmap.v -map <custom adder rules.v>; opt`, followed by abc
<daveshah> rather than trying to extract them after doing synthesis to gates
<ZirconiumX> Yeah, I figured I'd need to do something like that
<ZirconiumX> I'm wondering what other MSI chips I could add; the 74xx series has synchronous counters, for example,
<ZirconiumX> But I'm not sure what kinds of things Verilog usually emits
<daveshah> I believe Yosys has some support for mapping counters, it's used in the Greenpak4 pass
<ZirconiumX> I guess the best way of testing the impact of this kind of thing is a large Verilog library that Yosys can synthesize
<tpb> Title: yosys-bench/verilog/benchmarks_large at master · YosysHQ/yosys-bench · GitHub (at github.com)
<ZirconiumX> daveshah: Does Yosys not handle `$error`?
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<daveshah> ZirconiumX: I think https://github.com/YosysHQ/yosys/pull/1077 should have added support for that
<tpb> Title: elaboration system tasks by cliffordwolf · Pull Request #1077 · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> `yosys -V
<ZirconiumX> ` gives Yosys 0.8+531 (git sha1 d4f77d40, clang 6.0.0-1ubuntu2 -fPIC -Os)
<ZirconiumX> I'm getting a lot of `ERROR: syntax error, unexpected TOK_ELAB_TASK` while trying to parse the ethernet benchmark though
<daveshah> I think this is a recent regression, Yosys used to ignore them in this context (as is correct for a synthesis tool), but now tokenises them and then fails to ignore them in the parser (because it supports them in `generate` contexts now)
<ZirconiumX> Bug report?
<daveshah> Looks like https://github.com/YosysHQ/yosys/pull/1086 should fix it
<tpb> Title: Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks) by udif · Pull Request #1086 · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> Guess we'll have to wait for Clifford to get round to reviewing it
<daveshah> I've added a comment to try and speed that up...
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<ZirconiumX> daveshah: So, I've been reading the techmap documentation, and the example techmap implementations. If I want to insert a full adder, do I use (* techmap_celltype = "$add" *}
<ZirconiumX> ?
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<daveshah> ZirconiumX: Yes, however, you'll have to make sure you run techmap before alumacc in that case
<daveshah> alumacc converts arithmetic to more flexible, but more complicated `$macc` amd `$alu` cells (which are probably better suited to mapping things like FPGA carries than discrete chips)
<ZirconiumX> Is a $macc a multiply-accumulate unit?
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<daveshah> I think so, although I've never worked out it's exact semantics
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<ZirconiumX> daveshah: Is it worth having an early and late techmap pass? It seems useful to early-convert $add (74283) and $eq/$ne (7485/7485 with inverter), but late-convert things like counters etc?
<daveshah> Yes, definitely
<ZirconiumX> "early" and "late" being "before synth" and "after synth"
<ZirconiumX> Can techmap synthesize a $ne out of a $eq?
<ZirconiumX> (assuming they are what I think they are)
<daveshah> You might need to play around a bit, but I think that should be possible
<daveshah> Best route might be to take advantage of techmapping being recursive
<daveshah> So you write one rule that maps $ne to $eq, and another that maps $eq to logic
<daveshah> *to chips
<ZirconiumX> The 7485 is actually quite versatile; you can use it as a comparator too
<ZirconiumX> Presumably you'd need to infer that though
<daveshah> Might be able to map $lt and $gt
<daveshah> If you haven't found it already, https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simlib.v contains models for all the built in high level cells
<tpb> Title: yosys/simlib.v at master · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> daveshah: So to get this to work, I should build a model of the 7485 and then use a _TECHMAP_REPLACE_ for it?
<ZirconiumX> My verilog skills feel quite weak at the moment
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<daveshah> No, with techmapping you don't build a model of the thing you want to map to - instead you describe how to go from a Yosys cell type to the cell type you want to map to
<daveshah> This, for example, is an example of techmapping an `$alu` to a mix of soft logic and the hard Xilinx lookahead carry primitives: https://github.com/YosysHQ/yosys/blob/master/techlibs/xilinx/arith_map.v#L336-L353
<tpb> Title: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at github.com)
<tpb> Title: yosys/lut_map.v at master · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> So I'm allowed to pretend that a 74283 exists, even when I don't define it?
<ZirconiumX> Or whatever
<daveshah> You should probably have at least a "black box" - an empty model just specifying what pins are are inputs and what are outputs
<ZirconiumX> daveshah: So I just need my transformations to match the API of the equivalent simlib cell?
<daveshah> Yes
<daveshah> You don't have to handle all cases though, if you set a wire named _TECHMAP_FAIL_ to 1 then Yosys will fall back to its default implementation
<daveshah> e.g. https://github.com/YosysHQ/yosys/blob/master/techlibs/ecp5/arith_map.v#L36 tells Yosys not to use dedicated logic for adders smaller than four bits (in this case soft logic is more suitable)
<tpb> Title: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> So, for a 74283 (kinda thinking out loud), the maximum per-chip is 4 bit A + 4 bit B + carry in = 4 bit result + carry out
<ZirconiumX> So that would expand to recursion of some kind for greater widths, I'd imagine
<daveshah> Yes
<daveshah> The simplest way would probably be scaling both inputs to a common size, then using a generate for loop to instantiate the adders
<ZirconiumX> How would I chain carries between generate for iterations?
<daveshah> You can a wire for the intermediate signals
<daveshah> Sort of like how C and CO are used here: https://github.com/YosysHQ/yosys/blob/master/techlibs/ice40/arith_map.v#L43
<tpb> Title: yosys/arith_map.v at master · YosysHQ/yosys · GitHub (at github.com)
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<ZirconiumX> Verilator is being helpful as ever >.>
<tpb> Title: [SystemVerilog] module \74283 (A, B, CI, S, CO); input [3:0] A; input [3:0] B; input CI; o - Pastebin.com (at pastebin.com)
<ZirconiumX> Verilator complains here
<ZirconiumX> And using techmap on it infinite loops
<ZirconiumX> Though I realise there's obvious bugs
<ZirconiumX> I'm not sure how to pad the input and output buffers though
<ZirconiumX> Ah, a buffer
<ZirconiumX> I think
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<daveshah> ZirconiumX: you need to add `(* blackbox *)` to the 74283 model
<daveshah> Otherwise Yosys looks inside it, which you don't want in this context (because it will recursively techmap the add inside it)
<ZirconiumX> That makes sense
<daveshah> Normally, the idiom is to put all the sim models in a separate Verilog file to the techmap rules, and read that file in Yosys with read_verilog -lib
<daveshah> That implies blackbox on all the sim models
<daveshah> I'm also not sure if _TECHMAP_REPLACE_ will work here
<daveshah> It's intended for 1:1 techmapping, might cause problems when you map to more than one cell
<daveshah> I'd name the instance something else meaningful like adder_i
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<tpb> Title: (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - Pastebin.com (at pastebin.com)
<ZirconiumX> daveshah: How does this look?
<ZirconiumX> (I just noticed CARRY; I'll remove it)
<ZirconiumX> This should have a carry-in, but I don't know what to set it to
<ZirconiumX> A_SIGNED ^ B_SIGNED?
<daveshah> Yes, that makes sense
<ZirconiumX> Though, a value being signed or not does not imply whether it's positive or negative
<daveshah> Hmm
<daveshah> Actually, I think just leave CIN at zero
<daveshah> Also, might need a temporary signal for Y, otherwise it will go out of bounds
<ZirconiumX> Hm?
<ZirconiumX> I'm mostly just translating from the iCE40 arith_map.v
<daveshah> eg. have a YY signal of width WIDTH, then do `assign Y = YY[Y_WIDTH-1:0];`
<daveshah> Line 32 might go out of the bounds of Y when width isn't a multiple of four otherwise
<ZirconiumX> Should A_conv and B_conv be WIDTH instead of Y_WIDTH too?
<daveshah> No, that doesn't matter, the upper bits of A and B don't matter
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<ZirconiumX> daveshah: https://pastebin.com/UcPqn0T8
<tpb> Title: [SystemVerilog] (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - Pastebin.com (at pastebin.com)
<ZirconiumX> Yosys is complaining about line 42
<daveshah> wire [WIDTH-1:0] YY = Y_buf; should be the other way round
<daveshah> Y_buf = YY;
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<ZirconiumX> daveshah: But then YY isn't defined, right?
<daveshah> Ah yes, you'll also need to change the definition of Y_buf to define YY instead
<ZirconiumX> https://pastebin.com/C1EJx0ZC <-- I fixed the assign Y = Y_buf line instead
<tpb> Title: [SystemVerilog] (* techmap_celltype = "$add" *) module _80_74283_add (A, B, Y); parameter A_ - Pastebin.com (at pastebin.com)
<ZirconiumX> Yosys no longer complains at least
<daveshah> You can get rid of Y_buf altogether, as you're now just using YY and Y, which is fine
<daveshah> Remove Y_buf and just do wire [WIDTH-1:0] YY;
<ZirconiumX> What about A_buf and B_buf?
<ZirconiumX> Some stats, if you want a laugh
<daveshah> If you drive AA and BB from the `$pos` looks like they can be removed too
<ZirconiumX> Before, to go through my benchmark of various things, you'd need 7,340 ICs
<ZirconiumX> Now that Yosys recognises the 74283, you now need only 4,237
<daveshah> Very nice!
<daveshah> What is your synthesis script?
<ZirconiumX> read_verilog $<; hierarchy -auto-top; read_verilog -lib ../74_models.v; techmap -map ../74283.v; s ynth -run :fine; techmap -map +/techmap.v; opt; dfflibmap -liberty ../74series.lib; abc -liberty ../74series.lib; te e -o $@ stat
<ZirconiumX> Plus or minus awkward formatting (thanks Vim)
<daveshah> Try running `proc; opt; wreduce; opt` before mapping the 74283
<daveshah> It might reduce the width and number of adders slightly
<ZirconiumX> I appear to be leaking some $mem cells
<ZirconiumX> Your pre-map optimisation seems to bring the number of ICs way back up to 6,231
<ZirconiumX> (still less than before, at least)
<ZirconiumX> Yeah, your optimisation leaks $mem cells
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<daveshah> Oh, that's odd
<daveshah> What if you add `flatten` between `proc` and `opt`
<ZirconiumX> Still leaking $mem cells, but now we're down to 3,010 ICs
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<ZirconiumX> (PicoRV32 is now 1,018 ICs; it was 2,003 yesterday)
<daveshah> Try running `opt - full; memory_map; opt -full` after `synth -run :fine`
<daveshah> Right now nothing in that script is actually mapping memory to logic
<daveshah> *`opt -full`, no space between - and full in either case
<ZirconiumX> No more leaking $mem cells
<ZirconiumX> But one of the example benchmarks doesn't synthesize
<ZirconiumX> Looks like I messed up the adder?
<ZirconiumX> ERROR: Output port smartbextdep.$techmap\smartbextdep_direct_inst.decoder.pps_core.$add$../benchmarks/smartbextdep.v:245$1677.slice[0].adder_i.CO (\74283_1x1ADD4) is connected to constants: 1'x
<daveshah> ZirconiumX: Make C `WIDTH:0` rather than `Y_WIDTH:0`
<daveshah> in the techmap rule
<ZirconiumX> Yep, that fixes it, thank you once again
<ZirconiumX> 5,051 ICs for the benchmark here
<ZirconiumX> But all of the benches build at least
<ZirconiumX> And we're still doing better than before
<ZirconiumX> Have I thanked you enough, daveshah? I'm not sure I have.
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