clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<tmbinc> Is there a plan to support SV's multi dimensional packed arrays? ("reg [3:0][3:0] data;")
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<ZirconiumX> Where's the best place to post problems I'm having with Icarus Verilog, given that I'm a Verilog newbie and the error messages are awful?
<ZirconiumX> Yosys accepts my code, Verilator accepts my code, but Icarus rejects it with a "malformed statement" error
<tnt> ##openfpga ?
<ZipCPU> Yeah, ##openfpga might be the best place
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<corecode> ac
<corecode> ops
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