clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> Would it be nicer to use negative edge triggered 'reset' compared to its positive edge triggered counterparts ?
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<ZirconiumX> Here's a probably quite cursed idea.
<ZirconiumX> Yosys supports reading Verilog, optimising it, and writing it as BLIF
<ZirconiumX> If you then use misII, which is a UCB tool from the 90's, you can read BLIF and turn it into 74-series logic
<ZirconiumX> "But why?"
<ZirconiumX> Good question
<tnt> Why cursed ? I mean, if you need some logic done in 7400 that could be a totally valid way to find a solution possibly better than what you can come up with manually.
<ZirconiumX> True, but it's a very hacky way of doing it
<tnt> Maybe yosys has a 74 series mapping library natively ?
<ZirconiumX> That's a question; how would you write one?
<tnt> no clue
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<ZipCPU> ZirconiumX: Check out the ABC pass. synch + abc can be used to map a design to a variety of simpler logic circuits, such as you might use with 74-series logic. It's not specific to it, but I think it should work
<ZipCPU> "But why?" My son came home from college a semester ago with a requirement to design a particular 7-seg display circuit from straight logic gates. It's a whole lot easier to design and test in Verilog. Why no use Verilog, formally verify it, and then map it to gates using Yosys?
<daveshah> ABC can natively map simple gates, for fancier gates you could write a Liberty file (like https://github.com/YosysHQ/yosys/blob/master/examples/cmos/cmos_cells.lib) to map to
<tpb> Title: yosys/cmos_cells.lib at master · YosysHQ/yosys · GitHub (at github.com)
<ZirconiumX> I want to experiment with designing and building a CPU out of 74-series logic
<daveshah> But neither of these approaches support multiple-output gates, so you'd still be mapping gates rather than chips
<daveshah> i.e. you won't get a minimum-chip solution
<ZirconiumX> And, yeah, formal verification would be a bonus
<ZirconiumX> daveshah: Maybe you could approximate it by tuning the area settings
<daveshah> Yes, you could
<ZirconiumX> For example you can fit two 4-input muxes in a 74153, but only one 8-input mux in a 74151
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<ZirconiumX> daveshah: So do I need to make an equivalent cell for AND/ANDNOT/whatever, or do I make my own cells and let ABC figure it out?
<daveshah> ZirconiumX: I believe ABC needs three cells minimum: buffer, NOT and a logic gate (don't think the kind of gate matters much)
<daveshah> Otherwise it won't be happy
<ZirconiumX> Do they need to explicitly be named BUF/NOT/etc?
<daveshah> No, only the function matters
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<ZirconiumX> PicoRV32 apparently synthesizes to 398 7400 gates (so 99 ICs), and 93 7404 gates (so 16 ICs)
<daveshah> That seems very low
<daveshah> Maybe that isn't mapping the memory for some reason
<daveshah> *register file
<_vince> any comments on the chip stats? what's the most common chip in that circuit?
<ZirconiumX> Since it only currently understands the 7400, 7404 and 74367, don't expect miracles
<daveshah> The register file should need at least 1024 bits of state, so something must be going wrong
<_vince> hand optimizing 74s is fun ZipCPU probably why they are making him do it
<_vince> i had those kinds of exercises in high school electronics
<_vince> definately a crude 7segment clock was a topic but with a lot of help - we didnt have to design everything
<_vince> or was it that there was a 7s driver
<_vince> with BCD input or something
<ZirconiumX> Yeah, abc does not like multi-output gates
<ZirconiumX> I got an assertion failure in Yosys
<ZirconiumX> (why do I keep breaking this poor, poor program?)
<ZirconiumX> daveshah: `hierarchy` appears to be pruning picorv32_regs?
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<daveshah> I think picorv32_regs is an example of an external register file, picorv32 will use a built in one by default (set by a macro)
<daveshah> So I doubt that is the problem
<daveshah> You probably want `hierarchy -top picorv32; flatten`
<ZirconiumX> Okay, that seems more reasonable
<ZirconiumX> 3,722 7400 ICs, 579 7404 ICs, 6 74367 ICs
<daveshah> I think you'll also need to map DFFs seperately - see `dfflibmap`, `abc` in this context will only map combinational logic
<daveshah> That sounds about right
<ZirconiumX> So presumably for DFF I need to include D flip-flops?
<daveshah> Yes, and `dfflibmap` will map them seperately
<ZirconiumX> Does it expect each flop to have its own clock?
<daveshah> Yes - even though this isn't actually true for FPGA flows, usually this would be resolved in placement down the chain
<ZirconiumX> Gonna be fun finding an equivalent chip then
<daveshah> However, if there is only one clock in the design (as is the case with picorv32) then all flops will use that clock
<daveshah> Yosys won't create clocks out of nowhere
<ZirconiumX> There's the '574, but that only have one clock for 8 bits
<daveshah> That will be fine
<daveshah> I struggle to think of a design that has one clock domain for fewer than 8 bits...
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<ZirconiumX> So after adding a '574, dfflibmap is still complaining about unmapped cells
<ZirconiumX> DFFSR, which I think means a set-reset flip-flop?
<ZirconiumX> And also things like $_DFF_NN0_
<ZirconiumX> daveshah: ^
<daveshah> Is this with picorv32? These would be DFFs with async set/resets
<daveshah> Which I didn't think picorv32 had
<ZirconiumX> Yes, it is
<tpb> Title: 5. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty - Pastebin.com (at pastebin.com)
<daveshah> Ah it's only saying it didn't find these cell types in the library
<daveshah> But in this case it shouldn't need to map any of them
<daveshah> You can check by running `stat` after `dfflibmap`
<daveshah> This will show if there are any of these DFF types left unmapped
<tpb> Title: 7. Printing statistics. === picorv32 === Number of wires: - Pastebin.com (at pastebin.com)
<daveshah> Looks good, looks like it mapped all the DFFs
<ZirconiumX> There is something quite amusing about this; using Yosys to design 1970's era logic
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<tpb> Title: 7. Printing statistics. === picorv32 === Number of wires: - Pastebin.com (at pastebin.com)
<ZirconiumX> 7,583 cells
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<ZirconiumX> I can synthesize VecRiscV too
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<ZirconiumX> *VexRiscV
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<ZirconiumX> ZipCPU: So it seems like formally verifying a CPU made out of 7400 logic might actually be possible
<ZirconiumX> Although the "single output pin" problem is fairly crippling
<ZirconiumX> Also dfflibmap does not like the idea of output-enable bits
<ZipCPU> ;)
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