kraiskil has quit [Read error: Connection reset by peer]
kuldeep_ has joined #yosys
kuldeep has quit [Ping timeout: 240 seconds]
emeb_mac has quit [Ping timeout: 255 seconds]
jakobwenzel has joined #yosys
jakobwenzel has quit [Quit: jakobwenzel]
jakobwenzel has joined #yosys
m4ssi has joined #yosys
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
citypw has quit [Ping timeout: 258 seconds]
svenn has quit [Ping timeout: 255 seconds]
futarisIRCcloud has joined #yosys
_whitelogger has joined #yosys
adjtm has quit [Ping timeout: 250 seconds]
adjtm has joined #yosys
gnufan_home has quit [Ping timeout: 246 seconds]
proteusguy has joined #yosys
gnufan_home has joined #yosys
rohitksingh_work has quit [Read error: Connection reset by peer]
jevinski_ has quit [Ping timeout: 246 seconds]
jevinskie has joined #yosys
jevinskie has quit [Ping timeout: 255 seconds]
rohitksingh has joined #yosys
jevinskie has joined #yosys
citypw has joined #yosys
dys has joined #yosys
jevinski_ has joined #yosys
jevinskie has quit [Ping timeout: 245 seconds]
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
rohitksingh has quit [Ping timeout: 245 seconds]
gsi__ is now known as gsi_
citypw has quit [Ping timeout: 258 seconds]
jevinski_ has quit [Quit: My MacBook has gone to sleep. ZZZzzz…]
m4ssi has quit [Remote host closed the connection]
dys has quit [Ping timeout: 250 seconds]
X-Scale has quit [Ping timeout: 246 seconds]
X-Scale has joined #yosys
cr1901_modern has joined #yosys
rohitksingh has joined #yosys
emeb has joined #yosys
danieljabailey has quit [Ping timeout: 250 seconds]
rohitksingh has quit [Ping timeout: 258 seconds]
rohitksingh has joined #yosys
rohitksingh has quit [Ping timeout: 246 seconds]
rohitksingh has joined #yosys
indy has quit [Ping timeout: 250 seconds]
indy has joined #yosys
svenn has joined #yosys
futarisIRCcloud has joined #yosys
<bwidawsk>
ZipCPU: I'm just trying to understand a bit what's missing from the intel toolchain (I work for Intel and am a software dev just trying to figure out how things can be made better, if at all)
<bwidawsk>
like, if one wanted to not use quartus...
<bwidawsk>
I was surprised to see synth_intel was even available
<bwidawsk>
though I also don't quite grok the differences the underlying hardware makes at the netlist level
<sorear>
well if you tried to do synth_ecp5 you'd have a bad time because it would generate a netlist containing 4-LUTs and Lattice specific carry chain etc details
<sorear>
I don't think anyone who actively uses synth_intel is active on IRC; I haven't heard much about it one way or another
<elms>
bwidawsk: I haven't heard of any work on opening the steps after synthesis. So you would still need to use vendor tools for place and route and bitstream generation.
<tpb>
Title: GitHub - ZipCPU/arrowzip: A ZipCPU based demonstration of the MAX1000 FPGA board (at github.com)
<ZipCPU>
The problem I've had working with it is that I need a variety of hardware specific modules: primarily ODDR and PLL
<ZipCPU>
These modules aren't well documented, if at all
<ZipCPU>
Specifically, you need to figure out how to use: fiftyfivenm_io_obuf fiftyfivenm_io_ibuf fiftyfivenm_ff fiftyfive_ddio_out and fiftyfivenm_pll
<ZipCPU>
I think I'm close, but got distracted before being able to push the design across the finish line
<ZipCPU>
(It currently works without Yosys, just not with)
<bwidawsk>
well, I'm still very much in the learning and exploratory stage, so mostly just trying to figure out what's missing and if it's something we should look into doing
<bwidawsk>
if there's nice easy ways to get started with contributing, I'd love to (I spent most of my career working on linux graphics drivers, so this is quite a departure)
<ZipCPU>
This work is nearly all software work
<ZipCPU>
At least .... to get this design to work, it'd be all software work
<ZipCPU>
The hardware involved is pretty inexpensive as well at $30
<bwidawsk>
ZipCPU: so this is using quartus lite, I guess?
<ZipCPU>
Yes
<bwidawsk>
ZipCPU: okay, if you want to spend a few minutes giving a little write up of what needs doing, I can look. I'd like to get my feet wet with something tractable
<bwidawsk>
also, just curious are you programming the FPGA with the newish stuff that will land in linux 5.2?
<bwidawsk>
or using the closed drivers?
<ZipCPU>
This particular device I have programmed using libxsvf, since the Trenz drivers weren't working when I purchased my device
<ZipCPU>
So, here's the good news: all of the files Yosys works with are text files
<ZipCPU>
That includes the VQM file
<ZipCPU>
It's somewhat legible--there's no control codes, it's a file that describes structures, wires, and how they connect
<ZipCPU>
If you stare at it for a bit, you might get an idea
<ZipCPU>
However, my wife just got home from a week out of town, so ... if you'll excuse me, can I get back to you later?