clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<mithro> Why do some of the D flip flop models start with $_DFF and some start with $__DFF ?
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<daveshah> litghost: I've just asked Eddie to review
<daveshah> mithro: the $_ cells are "first class" gate-level cells that are supported throughout Yosys (eg for abc, opt, etc) whereas $__ cells are special-purpose cells
<daveshah> The $__ cells are generally only supported between one or a couple of passes and intended to be short-lived intermediate cells
<daveshah> The intention being you would then techmap them to arch-specific cells
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<litghost> daveshah: Thanks! I have trouble knowing who should be notified to take a look at reviews
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<mithro> daveshah: Is this a liberty file? -> https://github.com/YosysHQ/yosys/blob/master/techlibs/common/cells.lib ?
<tpb> Title: yosys/cells.lib at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> mithro: yes
<mithro> daveshah: Do you have a reference on how a liberty file works? I'm trying to understand what the function: "IQ" and ff(IQ, IQN) {} bits work?
<mithro> daveshah: Had that doc already open -- it only has one reference to "function:"... -- the ff Group section seems to have some of what I'm after but it is not the clearest.... Most of the docs I have so far are more interested in things like temp, voltage, process, etc...
<daveshah> ff(IQ, IQN) defines a flipflop with non-inverting output variable IQ and inverting output variable IQN
<daveshah> next_state specifies that the state after a clock edge is D
<daveshah> function gives the logic function for a pin
<daveshah> function: "IQ" means the pin simply mirrors the IQ variable (ie the FF state)
<daveshah> also FYI, you can combine read_liberty and write_verilog to convert liberty to verilog with Yosys
<mithro> daveshah: Is there a write_liberty?
<daveshah> No
<daveshah> It's not something anyone has had a use case before
<daveshah> A simple implementation probably wouldn't be too hard
<mithro> daveshah: Does adff means async dff? -> https://github.com/YosysHQ/yosys/blob/master/techlibs/common/adff2dff.v
<tpb> Title: yosys/adff2dff.v at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> Yes
<mithro> daveshah: So that is an Async DFF to Sync DFF techmap?
<daveshah> Yes
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<mithro> daveshah: eddie mentioned that ASIC designers mainly use liberty files for timing - does yosys already read timing information from liberty files at all?
<daveshah> mithro: No, but abc does (when used with Yosys it takes a liberty file directly rather than going through read_liberty)
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<mithro> daveshah: looking at module \$__DFFS_NN0_ (input D, C, R, output Q); TRELLIS_FF #(.GSR("DISABLED"), .CEMUX("1"), .CLKMUX("INV"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(C), .LSR(!R), .DI(D), .Q(Q)); endmodule
<mithro> daveshah: Doesn't that have 1 to many values in the flip flop name?
<daveshah> No
<mithro> What are the 3 values for?
<daveshah> Negative clock, negative set/reset, reset
<mithro> daveshah: The reset == value when negative set/reset occurs?
<daveshah> Yes
<daveshah> $__DFFS is a special synchronous set/reset DFF used by dff2dffs and the ECP5 techmap rules only
<daveshah> (S=synchronous)
<FL4SHK> so, I'm looking at the yosys GitHub README
<FL4SHK> the supported features of SystemVerilog lists interfaces... and modports
<FL4SHK> but it doesn't seem to synthesize the use of those features as module ports?
<FL4SHK> (yes, I know I've talked about this multiple days in a row now)
<mithro> daveshah: and $__DFFE_NN0 is the async set/reset version?
<daveshah> Yes, also with enable
<daveshah> FL4SHK: have you looked at the interface tests? Eg https://github.com/YosysHQ/yosys/blob/master/tests/svinterfaces/svinterface1.sv
<tpb> Title: yosys/svinterface1.sv at master · YosysHQ/yosys · GitHub (at github.com)
<daveshah> I don't know much about SV interfaces, so can't help much more than that
<mithro> daveshah: $__DFFE_NN0- Clock Negative, Enable Negative, Set/Reset - ???, Value on Reset 0 ??
<daveshah> Negative clock, negative set/reset, positive enable
<mithro> daveshah: the ECP only has positive enables?
<FL4SHK> wait
<FL4SHK> daveshah: wait
<FL4SHK> maybe I did something wrongly!
<FL4SHK> now I've got to give it a try again
<daveshah> mithro: No, but Yosys only supports positive enables iirc
<mithro> $_DFFE_PN_ (D, C, E, Q) - A positive edge D-type flip-flop with negative polarity enable. ?
<daveshah> Ah, looks like it only supports them without set/reset
<FL4SHK> daveshah: you may have made my day
<FL4SHK> thank you :P
<FL4SHK> that example is EXACTLY what I was looking for
<FL4SHK> ...how can I contribute more?
<FL4SHK> er, how can I contribute to yosys?
<daveshah> FL4SHK: is there anything in particular you want to work on?
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<FL4SHK> typedef, struct, enum
<daveshah> All of those would be great contributions
<FL4SHK> I've been working on my own compiler thing
<mithro> daveshah: I'm trying to build a table of flip flops at https://docs.google.com/spreadsheets/d/16yvScRkedOkPCRBSInFuHE_cUMD8Ls-b9KFmHocpC-o/edit#gid=0
<tpb> Title: Flip Flops - Google Sheets (at docs.google.com)
<FL4SHK> but contributing to yosys may actually be a better idea
<daveshah> mithro: DFFS/DFFSE are sync
<daveshah> DFFSR have both an async set and reset (and consequently don't map to most FPGA arches)
<FL4SHK> ...I do wish you could parameterize structs, btw
<FL4SHK> oh, yeah
<FL4SHK> one other thing: `type`
<FL4SHK> that's one thing that would be... useful
<mithro> daveshah: So, $_DFFSR_ should be async?
<daveshah> mithro: yes
<tpb> Title: yosys/simcells.v at master · YosysHQ/yosys · GitHub (at github.com)
<mithro> daveshah: Is it when there is a 0 or 1 in the truth table that it is async?
<daveshah> Or just look at the sensitivity list
<mithro> daveshah: It is async if both the clock and reset signal is in the sensitivity list?
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<daveshah> Yes
<FL4SHK> Is the open source form of yosys used for commercial applications, or do companies generally want to use the commercial version?
<daveshah> Depends what people are doing
<mithro> FL4SHK: Also depends on how you defined "commercial applications"
<daveshah> I know quite a few commercial users of open source Yosys (eg because they want a fully open flow)
<daveshah> Others need full VHDL and SV
<FL4SHK> I do FPGA dev professionally... and I'm concerned about there being a conflict of interest
<FL4SHK> ...don't want to lose my job
<daveshah> Probably fine if you don't work for a company that writes HDL frontends
<FL4SHK> I don't
<daveshah> But do check your T&Cs
<FL4SHK> I think I'm safe to *use* yosys, at least
<daveshah> The one thing to avoid is benchmarking - particularly publicly - against anything commercial you have at work
<daveshah> That's almost always banned in the EULA
<FL4SHK> I don't think I can even install yosys at work
<mithro> FL4SHK: You would have to ask your companies legal council - generally though the software is under a *very* permissive license
<daveshah> Yes, we don't require copyright assignment or anything like that
<FL4SHK> could we consider the version of SystemVerilog that the open source version of yosys implements to be a "custom language" on account of it not being anywhere near complete?
<FL4SHK> because... I may be safe, then
<mithro> FL4SHK: Google has released their "best practice for compliance with open source licenses" you can read if your interested -> https://opensource.google.com/docs/thirdparty/licenses/#notice
<tpb> Title: Licenses – opensource.google.com (at opensource.google.com)
<FL4SHK> mithro: it's actually not the open source licenses I'm concerned about
<daveshah> FL4SHK: well, Yosys does have a few non-standard extensions mostly for formal
<FL4SHK> right
<FL4SHK> or, at least for the Verilog side, anyway?
<FL4SHK> with -sv, isn't the formal stuff a subset of what SystemVerilog has?
<mithro> daveshah: _SR_ flip flops would be considered Async as they don't have any clocks, right?
<daveshah> Yes, it also adds a few convenience things like $anyseq, $anyconst
<FL4SHK> I think I'm at the very least safe to *use* yosys
<FL4SHK> so even if I don't end up contributing... hmmm
<daveshah> mithro: yes, although a latch might be a better description than a flipflop
<FL4SHK> latches are normally banned outside of ASICs, eh?
<daveshah> Yes
<daveshah> Although there is some interesting research opportunity into doing fully async stuff with FPGAs
<FL4SHK> ooh
<FL4SHK> neat
<FL4SHK> I didn't know that was happening.
<daveshah> It's not something you want to do unless you know exactly what's going on
<FL4SHK> Uh, right
<daveshah> FPGAs aren't glitch free in general
<FL4SHK> I've heard of async processors before.
<mithro> daveshah: I actually talked to some people at Archonix yesterday
<mithro> daveshah: They got out of the async FPGA game in the end :-(
<daveshah> Ah, that's a shame
<daveshah> I know a few people at my university are vaguely interested in async stuff
<FL4SHK> I think I will hold off on attempting to contribute to yosys for now.
<FL4SHK> but if someone else could... implement `typedef` and `enum`, I'd probably be really happy
<FL4SHK> `struct`s are FAR less necessary when you have `interface`s.
<FL4SHK> oh, here's a question I had: can yosys handle arrays on ports?
<FL4SHK> for -sv
<mithro> FL4SHK: There are quite a few people interested in support for those features... I think someone was even working on enums?
<FL4SHK> oooh
<FL4SHK> I can probably just wait for them to be implemented?
<FL4SHK> ...I'm shocked that `interface`s are, by the way, but pleasantly so.
<FL4SHK> I've been dying to be able to use `interface`s in formal
<FL4SHK> and in design
<FL4SHK> I was previously using Icarus Verilog to convert *its* subset of SystemVerilog into Verilog. That's how I originally did formal verification.
<mithro> daveshah: You aren't making it to latchup right?
<daveshah> No, exams :(
<mithro> daveshah: You have exams with a masters program? Or hasn't that started yet?
<daveshah> It's a integrated masters MEng
<daveshah> So 4 years with no bachelors
<mithro> daveshah: Ahh
<FL4SHK> What are you doing your master's in/
<FL4SHK> ?
<daveshah> Electronic and Information Engineering
<FL4SHK> ah. I have a bachelor's in mechanical engineering, and a master's in electrical engineering.
<FL4SHK> I just got the master's in December.
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<mithro> What would you call "sync verse async" ?
<ZipCPU> Async FF: always @(posedge i_clk, posedge i_reset) if (i_reset) Q <= 0; else Q <= D;
<ZipCPU> Sync FF: always @(posedge i_clk) if (i_reset) Q <= 0; else Q <= D;
<mithro> ZipCPU: I mean - like "Execution mode" or ?
<ZipCPU> I must be missing something. What "execution mode" are you talking about?
<mithro> ZipCPU: A flip flop can be sync or async right? What would you call this property of a flip flop?
<ZipCPU> Yes, I would call that a property of the flip flop
<mithro> ZipCPU: Yes but what is the name of this property of the flip flop? :-P
<ZipCPU> Usually its the "synchronous or asynchronous reset" proeprty
<ZipCPU> ... or some such
<ZipCPU> Some FF's also have an asynchronous set property as well
<FL4SHK> daveshah: so, out of curiosity, do interfaces instantiated in other interfaces work in yosys?
<FL4SHK> also, is there an option I need to set to make interfaces actually, uh, compile?
<FL4SHK> compile correctly*
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<FL4SHK> It just... appears that they're not with the version I got from GitHub
<FL4SHK> I get a lot of
<FL4SHK> Warning: Identifier `\MyInterfaceInstance.mysig_out' is implicitly declared.
<FL4SHK> things like this ^
<FL4SHK> and then it treats them as 1-bit things.