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<gundy>
Hi all; I have a design that has a "reg[31:0] buffer [0:7]" (line buffers for some sprite data), and yosys appears to be turning this into a $mem element which can't be placed. Is there any way I can nudge yosys not to do this for this particular set of registers?
<gundy>
The error I get during placement is "hardware.blif:24623: fatal error: unknown model `$mem'" (from arachne-pnr; nextpnr gives a similar error about timing data not being available for $mem).
<daveshah>
Putting (* mem2reg *) before it should fix it
<gundy>
OMG thank you!!! that may not specifically have _solved_ my problem, but it got me a *much* better error message and now I've got another lead to follow!!
<daveshah>
What is the problem now?
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<sorear>
this is a weird problem to have and i'd like to know how it turns out
<gundy>
Well, I got a new set of errors about multiple drivers for the registers, which reminded me that although I'm using always @(posedge clk) blocks in most places, I'd switched one block to negedge while trying to fix something else, and forgotten about it... and the negedge block was obviously impacting the way the memory was being used in such a way that it couldn't be synthesised nicely..
<gundy>
so entirely my fault
<gundy>
but I just couldn't figure out what was happening with the error messages I was seeing
<gundy>
so, yeah, you're an absolute star :)
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<sorear>
I really don't think icestorm should be failing in the way you observed
<daveshah>
The reason for the failure is simple - Yosys first maps the array of registers to a generic memory. But in this case its a very odd memory that can't map to BRAMs or registers, so it stays as a generic memory that causes PnR to die
<daveshah>
Coincidentally there's a similar issue in LSE, although that is worse because that happens with sensible RAM too sometimes
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<daveshah>
Not that that makes it right of course
<sorear>
IMO, pnr should never fail for any reason other than "you have too much routing congestion"
<sorear>
synthesis errors should be caught in synthesis
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