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<shapr>
ZipCPU: any familiarity with BlueSpec?
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<ZipCPU>
Marginal at best
<ZipCPU>
At least I know where to find (some) of the manuals.
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<awygle>
aren't most of the bluespec things standardized now?
<ZipCPU>
Could be, I just haven't found all of the manuals. daveshah has found more of them then I have.
<daveshah>
Nope, nowt to do with me
<daveshah>
never looked at bluespec before
<ZipCPU>
Ok, I must be confused then. I was thinking of the SB_ primitives
<ZipCPU>
I guess that's something different.
<mwk>
that was siliconblue
<ZipCPU>
Well ... I was close, they both had "Blue" in their name
<ZipCPU>
shapr: To answer your question: No.
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<shapr>
awygle: I dunno, I was talking to the author and they're using bluespec for several interesting projects
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<awygle>
shapr: when you say "bluespec" what do you mean? bluespec is a company iiuc, they made SystemVerilog. do they have a bluespec language also?
<awygle>
all i can find on their website is RISC-V IP...
<sorear>
there's a bluespec-specific HDL
<sorear>
i'm not sure if it's a SV derivative, something Haskell-based, or if they have both
<sorear>
they are one of the big Haskell shops, aside from relevance to hardware people
<awygle>
yeah the more i try to read about this the less clear it is so i should just shut my mouth basically
<awygle>
"Bluespec SystemVerilog (BSV) supports much, but not all, of SystemVerilog (SV) and also extends the language with features not present in SV. So neither is a full superset of the other, nor are they completely different. "
<shapr>
awygle: bet you still know more than I do about bluespec
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<shapr>
sorear: I got to chat with Lennart Augustsson at ICFP, asked him about the project he's working on now
<shapr>
at this point I now know that Groq and Google X are working on their own takes on Google's TPU, and that Jane Street is working on compiling OCaml to FPGAs for purposes I have not been able to discover.
<shapr>
Google X is using BlueSpec, Groq is using Haskell, but that's all the details I have.
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<keesj>
Hi
<keesj>
I am working on a hobby project creating a board based on iCE40UP5K-SG48 (I plan to used yosys and all the goodness) How do I find the mapping between physical pins and internal pin names? I see that the chip is supported and did find some references to pin names (and know it is documented in the Lattice documentation somwhere..) but U can't find it
<keesj>
plzzzz help :P
<keesj>
(is possible I would also like to see the mapping .. the same stuff for the global clock lines). Knowing what bank the pins are.. (same story)