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[scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±3] https://git.io/JUmqY
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[scopehal-apps] azonenberg c89d1f2 - WaveformArea: prevent trigger position arrow from going off screen. Fixes #31.
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[scopehal-apps] azonenberg closed issue #31: If trigger arrow is off scale, can't drag it to change trigger level - https://git.io/JUmqO
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[scopehal-apps] azonenberg closed issue #124: When adding a filter with X axis units that don't match the current group, split the current group horizontally - https://git.io/JJvPS
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[scopehal-apps] azonenberg commented on issue #124: When adding a filter with X axis units that don't match the current group, split the current group horizontally - https://git.io/JUmqg
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<azonenberg>
Thoughts on AD9739 as a DAC for the signal generator?
<azonenberg>
it's not JESD204B as far as i can see, it's parallel LVDS. Which might actually be a good thing
<azonenberg>
it means i could use a kintex7 FPGA and then still have a 10GbE port on it
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<azonenberg>
Since i could use normal GPIOs instead of SERDES to talk to it
<azonenberg>
It's 14 bit instead of 16 like the dac i was looking at before, but does 2.5 Gsps update rate so i could do up to 1.25 GHz bandwidth on the output
<azonenberg>
lain: what do you think?
<azonenberg>
watching TSP #158 and the tek AWG he's looking at uses it
<azonenberg>
not sure why i didn't see it on my previous component search
<azonenberg>
$73 each
<lain>
ohhh nice
<azonenberg>
Four of these would need 2.5 Gsps * 14 bits (rounding up to 16 to keep byte alignment) * 4 channels = 160 Gbps of data to keep fed
<azonenberg>
Which is a problem because that's way more than a ddr3 sodimm can put out
<azonenberg>
i could fall back to 2 channels or i could go multichannel memory
<azonenberg>
Aaaand i just did the math
<azonenberg>
each dac basically needs a whole I/O bank worth of LVDS, plus a few slow SPI lines, to keep it fed
<azonenberg>
the 7k160t has five banks of HR and 3 of HP, if i used all of the HP's i'd only have enough for one sodimm of memory
<azonenberg>
and then i'd be using one of the HR for ethernet and spi buses and boot flash and the other HRs for the DACs. But i wouldn't have enough ram to keep up
<azonenberg>
lain: Hypothetical architecture: dual FPGAs, 4 channels. Primary FPGA connects to the ethernet interface and 2 dacs, then has a GTX link to the second FPGA which runs the other two dacs, each fpga has a dedicated sodimm of ram
<azonenberg>
Can DNP the second fpga/ram/2 dacs to cut the BOM cost roughly in half
<azonenberg>
and make a 2 channel system
<lain>
sounds reasonable
<azonenberg>
ok i'll write this up in my notes. Not getting to it until post MAXWELL
<azonenberg>
but i want to have a plan
<Degi>
Hm dont they do 1.25?
<Degi>
Whats a GTX link?
<azonenberg>
GTX = kintex-7 SERDES
<Degi>
Neat
<azonenberg>
basically i'm proposing an architecture in which we have two almost identical FPGAs running two dacs each
<azonenberg>
except one of them speaks ethernet to the outside world and a custom protocol to the other fpga
<azonenberg>
and the other speaks the custom protocol only
<azonenberg>
99% of the RTL would be the same on both
<Degi>
Why does it say "Dual-port LVDS data interface Up to 1.25 GSPS operation" and "A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS."
<azonenberg>
layout would be basically copy pasted
<azonenberg>
The DAC has two 14-bit LVDS buses. 14 data @ 1.25 Gbps, clock @ 625 MHz
<Degi>
Lol that is the LVDS input rate
<azonenberg>
dac alternates fetching from one side and the other
<Degi>
That is nice
<azonenberg>
basically the bus is double width and half rate
<azonenberg>
In the TSP review shahriar says it's JESD204B which is incorrect
<Degi>
What does "1.25 GHz to 3.0 GHz in mix mode " mean
<azonenberg>
I think the dac has the ability to upconvert the output
<azonenberg>
so you have DC to 1.25 GHz output mixed with a carrier to shift it up to 1.25-3
<Degi>
And what is a "no fail-safe" lvds input heh
<azonenberg>
but i'm not that far along in the datasheet
<Degi>
Hm that is nice, though in the block diagram that isnt visible
<azonenberg>
Maybe it pairs with an external mixer?
<azonenberg>
or if you mix the two outputs together?
<azonenberg>
i havent got that far yet
<Degi>
Ah, it does some fun stuff which causes the baseband signal to be strongly reduced in intensity while the images mirrored by the sample rate stay strong, thus providing high frequencies.
<azonenberg>
yeah i was planning on just doing baseband mode from dc to 1.5 GHz
<Bird|otherbox>
Degi, I suspect it means that the receiver won't put out a defined logic level with floating or shorted inputs
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<Bird|otherbox>
(integral fail-safe on receivers is common nowadays, especially in more hostile applications such as RS-485 based fieldbuses)
<Bird|otherbox>
<Bird|otherbox> Degi, I suspect it means that the receiver won't put out a defined logic level with floating or shorted inputs <<re: your "no fail safe" comment on the LVDS input
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<azonenberg>
ok so i think tonight i'm gonna work on horizontal position control (loooong overdue)
<azonenberg>
And fixing #223
<azonenberg>
welp, today's job just got bigger
<azonenberg>
apparently setting probe attenuation and coupling in the UI never got implemented
<azonenberg>
the methods are there, and the "get" calls correctly highlight the radio buttons in the menu
<azonenberg>
but clicking the menus doesnt actually call the set method
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[scopehal] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JUm0q
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[scopehal] azonenberg opened issue #234: LeCroyOscilloscope seems to not work properly in pure logic analyzer mode (no analog channels enabled) - https://git.io/JUYqo
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[scopehal] azonenberg labeled issue #234: LeCroyOscilloscope seems to not work properly in pure logic analyzer mode (no analog channels enabled) - https://git.io/JUYqo
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[scopehal] azonenberg labeled issue #234: LeCroyOscilloscope seems to not work properly in pure logic analyzer mode (no analog channels enabled) - https://git.io/JUYqo
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[scopehal-apps] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/JUYme
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[scopehal-apps] azonenberg 247acb9 - OscilloscopeWindow: flush old waveforms when loading from a file, but properly detach new ones
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<azonenberg>
Sooo i'm planning to write a 25* SPI flash protocol decode
<azonenberg>
my thought at the moment is that it will have a total of 3 inputs
<azonenberg>
x1 SPI on DQ0 and DQ1 aka MOSI/MISO
<azonenberg>
and quad SPI on DQ[3:0]
<azonenberg>
the latter can be omitted if the controller doesn't support quad mode