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<DocScrutinizer05>
k
<DocScrutinizer05>
btw did you notice the similarities between the FET in 4 and an "ideal diode"
<DocScrutinizer05>
?
<wpwrak>
yes, there's a bit of that there
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<DocScrutinizer05>
I just wonder what's the ABSMAX for the sMCU
<DocScrutinizer05>
particularly regarding voltage on any pin vs VCC
<DocScrutinizer05>
my final design recommendation is: ADC/GPIO[1] - 3M3 - C1 - GND; [1] - schottky - VCC
<DocScrutinizer05>
the leakage current on ADC/GPIO is basically negligible resp no problem to probe for, after power return
<DocScrutinizer05>
simply charge again until C1 full, then switch to discharge and probe voltage
<DocScrutinizer05>
the temperature and thus leakage of the chip won't change in the timespan from battery change aka discharge, over probing residual charge on C1 after power return, to probing leakage after fully charging C1 after residual charge probing
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<DocScrutinizer05>
for 1uA@3V3 leakage current you got an equiv Z of 3M3, what a coincidence ;-)
<DocScrutinizer05>
so your ADC would still probe with a multiplier of 0.5, which is easy to determine after you charged C1 to VCC, *after* probing residual charge after batt swap
<DocScrutinizer05>
and 0.5 "prescaler" also leaves still enough precision in ADC
<DocScrutinizer05>
s/precision/resolution/
<qi-bot>
DocScrutinizer05 meant: "and 0.5 "prescaler" also leaves still enough resolution in ADC"
<DocScrutinizer05>
it's just one bit less
<DocScrutinizer05>
you could even get quarter-bit or even 1/8 bit resolution by polling at high speed and determinin time for first 1digit decrement vs time between 1st and 2nd 1bit decrement
<DocScrutinizer05>
you even can *completely* eliminate prescaler effects of GPIO leakage, by doing a PWM beween charge and discharge to keep C1 voltage steady
<DocScrutinizer05>
your C1 voltage is exactly Vcc * PWM ratio
<DocScrutinizer05>
how much better than this could any other design get?
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<DocScrutinizer05>
(and how much simpler, BOM wise and to evaluate)
<DocScrutinizer05>
wpwrak: ^^^
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<DocScrutinizer05>
((*completely* eliminate)) not only prescaler effects but also any nonlinearities in ADC
<DocScrutinizer05>
only thing you can't completely eliminate but only mitigate with PWM is ADC noise
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<DocScrutinizer05>
to be precise: s/Vcc/Vio/g
<DocScrutinizer05>
even when Vcc doesn't rapidly drop to 0V, it's still a given that the whole circuit is in a quasi static state without any variables, after MCU stopped working. So it should be highly repeatable
<DocScrutinizer05>
IOW discharge is still predictable (by calibration)
<DocScrutinizer05>
factory side calibration
<wpwrak>
the ADC is 16 bit. so i can make many ADC effects (not quite all, e.g., not non-linearity) vanish into bits that hold no useful value anyway ;-)
<DocScrutinizer05>
you do a test series discharge time vs capacitor voltage, create a tab and that should be good enough
<wpwrak>
(pre
<DocScrutinizer05>
at least for precision in the sub-second range during 60s
<wpwrak>
dictable) dunno. there are elements that may develop their own life before i can fully "neutralize" them. e.g., the OLED.
<DocScrutinizer05>
how long will that take? 1s, or less?
<wpwrak>
that's what i don't know :)
<DocScrutinizer05>
no matter if 1s or less, the effect on timing is negligible
<DocScrutinizer05>
definitely can't be larger than 1s of error
<DocScrutinizer05>
same for glitches
<DocScrutinizer05>
before trying to eliminate dirt effects, we need to consider if they matter at all
<DocScrutinizer05>
otherwise the cure will be much worse than the disease
<wpwrak>
if system leakage is in the order of 5 uA and we have about 50 uF of caps on the rail, a drop by 1 V would take 10 s
<DocScrutinizer05>
fine
<DocScrutinizer05>
and what are the variables in all this?
<DocScrutinizer05>
I mean, the variables you can't determine even at runtime
<DocScrutinizer05>
or even control at runtime
<wpwrak>
the MCU loses sight of things around 1.71 V, realistically much earlier, since we want to clean up and close shop as soon as we go significantly below 3.3 V
<DocScrutinizer05>
fine
<DocScrutinizer05>
then system is in a very well defined state from that moment
<DocScrutinizer05>
the only vatiable I see is temperature
<wpwrak>
component variations, component state. e.g., the OLED has its own DC-DC converter that can keep things alive for a while
<DocScrutinizer05>
so what? those won't change over lifetime of a particular device much
<DocScrutinizer05>
you control component state
<DocScrutinizer05>
that's the whole purpose of "closing shop"
<DocScrutinizer05>
if factory side (R&D) calibration isn't sufficient, user needs to do a onetime calibration for the device (if you don't want to do this at factory for each device)
<wpwrak>
not necessarily. e.g., i don't really know what's going on inside the OLED, and i eventually lose the ability to communicate with it. i can still command a reset, though, but i don't know how that affects residual charges and the things they drive
<DocScrutinizer05>
you can however instruct the display to switch on or off all pixels, as long as shop not closed yet
<wpwrak>
mmh. lemme check ...
<DocScrutinizer05>
which I am pretty sure has identical effect on component state on all the OLEDs you ship
<DocScrutinizer05>
there's no HRNG in OLED that creates massive uncertainties in component behavior
<DocScrutinizer05>
when one OLED acts in a particular way once, it will do twice under same (history of) conditions, and other identical OLED components will as well
<wpwrak>
there is a "quick" display off command. in fact, there are two, with not very clearly spelled out differences
<DocScrutinizer05>
if there are massive fluctuations between components of same bin, you need per-device calibration to cope with those
<DocScrutinizer05>
otherwise one time R&D 'calibration' will do
<DocScrutinizer05>
tbh I'd rather power on all consumers to pull Vcc to GND as fast as possible
<wpwrak>
of course, the more we clean up, the lower the leakage. so we're increasing that slope
<wpwrak>
yes, exactly ;-)
<wpwrak>
have some 100 uF anti-charge cap somewhere ;-)
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<DocScrutinizer05>
there are a number of nonlinear components like PTCs ;-) But honestly I'd not worry too much about all this, I'm pretty sure you can pull Vcc to GND in less than a second
<DocScrutinizer05>
or at least to a steady state of maybe 1V5 above GND
<DocScrutinizer05>
and you can do this very reproducibly
<DocScrutinizer05>
irrespective of any random effects based on history of the component behavior (aka commands issued before)
<DocScrutinizer05>
as I said, there's no HRNG in any of your components that would have massive impact on their behavior on power down
<DocScrutinizer05>
only variable is temperature, yet to get evaluated if it matters at all
<wpwrak>
you don't need a HRNG. it's enough if there is something that can be in different internal states you don't control. that's what i'm worried about.
<DocScrutinizer05>
particularly system behavior from 1V5 down to 0V on Vcc is pretty reproducible
<wpwrak>
and i can't actually test such things before having a number of devices
<DocScrutinizer05>
you hardly have *any* devices with different internal stages after receiving same sequence of commands
<wpwrak>
hence i prefer a "safe" design that itsn't at risk of needing a redesign at that point
<DocScrutinizer05>
you don't need several devices, random different internal stages are a problem of *one* device
<wpwrak>
i don't really have time for elaborate transitions. e.g., the OLED has transitions that are specified to take some 100 ms. i can't risk waiting for such things.
<DocScrutinizer05>
which you can test right away. and designing for a 100% safe circuit no matter which possible nasty properties components might have is not possible
<DocScrutinizer05>
huh? don't you know in which state the OLED is, before as well as after such transition?
<DocScrutinizer05>
isn't that deterministic?
<wpwrak>
(test right away) naw, there are several new components in the new design for which no prototype exists yet
<DocScrutinizer05>
I just can tell you you're massively overengineering this
<DocScrutinizer05>
if time is SOOOOO important, add a cmos clock and a goldcap
<wpwrak>
i know the "high-level" state before and i know the state after. what happens in the middle, duh. inside the high-level state, there are internal sub-states that are hidden from me.
<wpwrak>
heh ;-)
<wpwrak>
may not be so difficult to be able to support page 3 (diode) and page 4 (fet) design in the same circuit, with a minor placement change
<DocScrutinizer05>
both add more complications than they solve
<wpwrak>
so you don't like the diode anymore ?
<DocScrutinizer05>
my final design recommendation is: ADC/GPIO[1] - 3M3 - C1 - GND; [1] - schottky - VCC
<wpwrak>
page 3 is pretty much that, except that i add a lower R between C1 and ADC/GPIO
<DocScrutinizer05>
[2016-03-27 Sun 13:49:10] <DocScrutinizer05> I just wonder what's the ABSMAX for the sMCU - particularly regarding voltage on any pin vs VCC (when Vcc = 0V and capacitor 3V)
<DocScrutinizer05>
and no, your design is massively different in that respect to mine
<wpwrak>
okay, that's a fair point
<wpwrak>
the absmax is the usual vdd + 0.3 V but there is no clamping diode. so i don't quite know what happens.
<DocScrutinizer05>
@ occasional lurkes: Vdd is another synonymous name for Vcc
<wpwrak>
what really worries me in your design is the huge resistance amplifying even the tiniest GPIO leakage
<wpwrak>
well, i guess i could always raise C1 to 47 uF or such :)
<DocScrutinizer05>
as I elaborated you got the precision of a 1bit delta-slope converter ( precision of your timebase) for ADC when you do that PWM pattern I suggested. Completely irrespective of any leahage current however large or small
<DocScrutinizer05>
well, actually the precision limit is the noise and resolution of the ADC, but *not* any prescaler formed by resistors and leakage current
<DocScrutinizer05>
when you switch 8PWM) between 25% charging via R from Vcc and 75% discharging via R to GND and that keeps your voltage staedy, then you know your capacitor has exactly 25% of Vcc resp Vio
<DocScrutinizer05>
s/8/(/
<qi-bot>
DocScrutinizer05 meant: "when you switch (PWM) between 25% charging via R from Vcc and 75% discharging via R to GND and that keeps your voltage staedy, then you know your capacitor has exactly 25% of Vcc resp Vio"
<wpwrak>
i don't see how PWM would help with measuring. charging/discharging is not a problem, since we have low impedance anyway
<DocScrutinizer05>
see above
<DocScrutinizer05>
my final design recommendation is: ADC/GPIO[1] - 3M3 - C1 - GND; [1] - schottky - VCC
<DocScrutinizer05>
3 components, one GPIO
<DocScrutinizer05>
capacitor voltage probable to 0.1% precision almost irrespective to size of R
<DocScrutinizer05>
no overvoltage issues at GPIO (when Vdd = 0V). Immune tio glitches
<DocScrutinizer05>
yes, it still has the 'problem' of Vdd not falling to 0V for 20s, but we discussed that thoroughly during last 30min, it can get taken care of by software design
<DocScrutinizer05>
by fast discharge as well as R&D or factory (per unit) calibration
<DocScrutinizer05>
one particular OLED won't suddently start to behave randomly differnet, when you propperly "initialize" it during shutdown
<DocScrutinizer05>
when there are N different states the component can be in, and you can't transition fast between them, all you need to do is to know the current state and apply the according calibration
<DocScrutinizer05>
there is no HRNG
<DocScrutinizer05>
your circuit is mostly deterministic
<wpwrak>
(see above) hmm, that would help with the part of the error that is because of component variation. i wouldn't help with error due to chip temperature. i wonder if we can do such precise temperature compensation. after all, the possible V difference would be basically the whole measurement range, with the leakage current going through 3.3 MOhm.
<DocScrutinizer05>
you know the state it's in so you can predict how it behaves
<DocScrutinizer05>
you still didn't grok the PWM thing?
<wpwrak>
i think i get the PWM thing: you charge to a well-known voltage, then measure, and thus calculate the leakage current
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<DocScrutinizer05>
when you switch (PWM) between 25% charging via R from Vcc and 75% discharging via R to GND and that keeps your voltage staedy, then you know your capacitor has exactly 25% of Vcc resp Vio - capacitor voltage probable to 0.1% precision almost irrespective to size of R and leakage current
<DocScrutinizer05>
no
<DocScrutinizer05>
I do PWM charge/discharge to keep the ADC at a steady level that was the value when first probing the voltage of C1
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<DocScrutinizer05>
leakage current: irrelevant doesn't show up in equation
<DocScrutinizer05>
same for size of R
<wpwrak>
how does a PWM with fixed ratio hold an arbitrary initial voltage ?
<DocScrutinizer05>
PWM= 42.4711%, so voltage on C = Vio/Vcc * 42.4711%
<wpwrak>
sure. but how does this help with _measuring_ ?
<DocScrutinizer05>
the trick is to adjust the PWM so it has same average voltage as C
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<wpwrak>
you're talking about a second RC circuit, for the PWM ?
<DocScrutinizer05>
no
<DocScrutinizer05>
with a given capacitor voltage (to probe) of 42.4711%, you first get a ADC that results in value 12345, then you start with a PWM of 50% (you can optimize by guessing the needed PWM from 12345) and watch the ADC. It will go up to 12350 or whatever, so you know your 50% are too high and you turn it down to 45%
<DocScrutinizer05>
redu until your ADC again shows 12345 and your PWM vill be 42.4711%
<DocScrutinizer05>
redo even
<wpwrak>
ah, i see. so 2 (or more) measurements
<DocScrutinizer05>
all percentages of voltage with respect to Vio/Vdd
<DocScrutinizer05>
yes, multiple measurements
<wpwrak>
temperature may still be an issue. if the MCU is actively moving things around, that may change the chip temperature a little. and since we're extremely temperature-sensitive there, ...
<wpwrak>
but okay, that could probably be compensated, too
<DocScrutinizer05>
the only variables determining precision are: the *relative* precision of ADC (noise and resolution), Vdd and your timer for PWM
<wpwrak>
e.g., meas(temp), meas(Vc1), meas(temp), then do the PWM routing, also all the while measuring the temperature
<wpwrak>
s/routing/routine/
<DocScrutinizer05>
how much could temperature change during 2 minutes? also where is temperature realyl coming in here. For sure not for probing, probbaly for Vcc discharge though
<wpwrak>
sure for probing. don't forget that it can go up to 1 uA over a 100 C range. so that's about 1% of the measurement range for each C, assuming the change is linear
<DocScrutinizer05>
hmm?
<wpwrak>
we'll be trying to measure differences < 1% of the range
<DocScrutinizer05>
so?
<wpwrak>
range = [0, 3.3 V]. 1 uA * 3.3 MOhm = 3.3 V, 100% of the range
<DocScrutinizer05>
you're confused :-)
<wpwrak>
so even slight temp changes can throw us off
<DocScrutinizer05>
no, leakage current doesn't show up in the equation
<wpwrak>
max leakage is 25 nA at 25 C and 1 uA "over full temp range", i.e., at 125 C
<DocScrutinizer05>
this "meter" is completely immune to leakage current
<wpwrak>
but only if you're assuming constant leakage
<DocScrutinizer05>
yes
<wpwrak>
what i'm saying is that it changes
<DocScrutinizer05>
during measuring period
<DocScrutinizer05>
which is <1s
<DocScrutinizer05>
I don't see how temperature could change during this period of time
<DocScrutinizer05>
maybe it helps ro check wikipedia for sigma-delta ADC
<wpwrak>
hmm, i get about 0.7 C, assuming we draw ~2 mA on average. that would be okay.
<DocScrutinizer05>
this is a modified sigma-delta scheme
<wpwrak>
i understand the process, my concern is the effect of leakage changing during the process. but it seems that the change would be relatively small.
<DocScrutinizer05>
you can bet on the effect being too small to calculate it without help of an electronic calculator ;-)
<DocScrutinizer05>
it will be serveral magnitudes lower than your demanded precision of 1%
<DocScrutinizer05>
_several_
<wpwrak>
i get about 1 C = 1%, so, zero magnitudes :) still, that's already
<DocScrutinizer05>
how's the chance for the low power chip to heat up 1°C during less than 1s, in a semi-steady state 2 or 3 seconds after power up
<DocScrutinizer05>
your stability of Vdd is a more concerning issue regarding ADC precision
<DocScrutinizer05>
after all we use Vdd as reference voltage here, all the time
<DocScrutinizer05>
dunno if your ADC has an internal stabilized refernce voltage so you could use ADC to determine actual voltage of Vio
<wpwrak>
Vcc should be pretty stable, and when we ramp down, we already assume we fall rapidly, right ? :) i'd set the low voltage interrupt close to 3.3 V, so te MCU reacts within some 10% of the range.
<wpwrak>
and yes, the ADC has a bandgap reference, too
<wpwrak>
they pretty much all do nowadays ;-)
<DocScrutinizer05>
so you can probe the real voltage during charging, while same time pulling ADC/GPIO high and probing it
<DocScrutinizer05>
and you also can probe the real low voltage on ADC/GPIO = L
<DocScrutinizer05>
now you have a very precise Vhigh and Vlow and a very precise PWM timing, you're set
<DocScrutinizer05>
your capacitor voltage is Vlow + PWM% * (Vhigh - VLOW)
<DocScrutinizer05>
which for 100% PWM = Vhigh ;-)
<DocScrutinizer05>
aka charging
<wpwrak>
Vlow (i.e., ADC = 0 V) will be close enough to GND, even if we go for the full 16 bit resolution :) 1 uA * 100 Ohm ~ 2 * 3.3 V >> 16 ;-)
<wpwrak>
(10 or 12 bit probably makes more sense)
<DocScrutinizer05>
well, you have a load current through discharging, via the 3M3, so your Vlow might be higher than 0V00
<wpwrak>
yes, by up to 3.3 V / 3.3 MOhm = 1 uA :)
<DocScrutinizer05>
actually it depends on Vcapacitor too
<DocScrutinizer05>
aaah ok
<DocScrutinizer05>
yes, right
<DocScrutinizer05>
Vcc stability during ramp-down is no problem, after all you're either in charging mode and the slight variation in Vcc will be less than a glitch for this circuit, or you already entered discharging mode where Vcc doesn't matter at all
<DocScrutinizer05>
we also have one 'problem' with this circuit: charging takes as long as discharging, so the recovery window after power return is rather long. No two battery swaps in sequence
<DocScrutinizer05>
well, can get mitigated in software
<DocScrutinizer05>
actually you just need to write history (with timestamps) to storage, to have the complete picture and do the "right thing"
<DocScrutinizer05>
histroy can get deleted as soon as capacitor is supposedly recharged to 100% after a few minutes of charging time
<wpwrak>
whitequark: a wild search HKG-LPA, suggests ~USD 1k (in argentina) with 25h10 + 20h15, with KLM and AF. may 5, june 1. (since this seems to be a month-long event ?)
<wpwrak>
then you just need a boat to make it to lanzarote :)
<whitequark>
hm, then my search engine fucked up
<DocScrutinizer05>
wpwrak: I'm fixing the code
<DocScrutinizer05>
rather, the algo, I'm prolly fscking up the code ;-)
<wpwrak>
whitequark: maybe don't search from your iphone ;-)
<dcht00>
DocScrutinizer05 good to see we have friends everywhere :)
<dcht00>
if you send an email saying hi at a random time that'd make my day
<whitequark>
wpwrak: I don't have an iphone, nor did I search from a smartphone...
<wpwrak>
whitequark: hehe ;) i was referring to iphone users sometimes getting shown more expensive offers than the rest of humanity
<dcht00>
quick search from me:
<dcht00>
12h + 1200€ to go from Hong Kong to Germany
<whitequark>
ahhhh, I had no idea
<wpwrak>
DocScrutinizer05: (algo) i used a simple one to illustrate the concept. in real life, there would be more non-linear components, but factoring them in would just make it harder to see the basic idea
<dcht00>
from there it's another 5h to Lanzarote, with some layover
<DocScrutinizer05>
the basic idea needs fixing
<dcht00>
but ....... I honestly wouldn't encourage you to spend 3 grand to travel here :)
<dcht00>
donations of 1% of that are very welcome though
<dcht00>
:)
<wpwrak>
whitequark: it's lanzarote that makes it expensive. to las palmas it's about 1/2 of hkg-lanzarote
<whitequark>
mhrm
<wpwrak>
(didn't try to vary dates. maybe that would change it, too)
<wpwrak>
but it;s probably best to fly to gran canaria, then make the last hop with a local LCC, or maybe a ferry if that's common there. the local organizers should know
<wpwrak>
the usual travel sites sometimes don't even list the LCCs, so you miss the most efficient routes
<DocScrutinizer05>
wpwrak: this code is still full of bugs and mess, but it demonstrates the idea
<wpwrak>
no "* 100%" in c-ish syntax ;-)
<DocScrutinizer05>
huh?
<wpwrak>
that's very slow convergence. mine tries to converge much faster. that's especially imporant considering that also PWM goes through 3.3 V, so it may take a lot of time to change Vc1.
<DocScrutinizer05>
???
<DocScrutinizer05>
yours doesn't converge any way, it's a one time calculation that tries to figure leakage current
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<wpwrak>
anyway, in think the main idea is to adjust C1 through PWM and then measure what we got. whether we then operate with deltas or stepwise approximation, is a second order problem
<DocScrutinizer05>
no, the idea is to NOT adjust C1 and keep it at a given ADC value instead. Finmd the PWM duty that matches this condition
<wpwrak>
well, a bit like euler's method :)
<DocScrutinizer05>
a bit like sigma-delta ADC
<wpwrak>
but you do adjust C1
<DocScrutinizer05>
delta-sigma?
<DocScrutinizer05>
only temporarily until it changes one tick on ADC so I know if PWM is too high or too low. Then I immediately resore it to its original voltage
<DocScrutinizer05>
C1's voltage is meant to keep constant (+-2 ticks) during complete PWM-ADC
<DocScrutinizer05>
while PWM gets adjusted so it keeps C1 voltage at that ADC level for long time (NUM_SAMPLES = 20)
<DocScrutinizer05>
you can make NUM_SAMPLES = 2000 if you like
<DocScrutinizer05>
ooh, and that code for sure is no C syntax, rather a tad pythony
<DocScrutinizer05>
only temporarily until it changes one tick on ADC <(abs(adc_t - adc_0) > NOISE_THRESHOLD) ; line25> so I know if PWM is too high or too low <(adc_t - adc_0) >0; line28>
<DocScrutinizer05>
Then I immediately restore it to its original voltage <lines 29-32, 34-37>
<DocScrutinizer05>
lines 31, 36 are >> // adjust duty TODO: short hack, optimize!<< and actually need optimization
<DocScrutinizer05>
there Euler comes in
<DocScrutinizer05>
N +- N/2 +- N/4...
<wpwrak>
those duty++ and duty-- should be outside the loops, right ?
<DocScrutinizer05>
no
<DocScrutinizer05>
not really, I kept them inside the loops since duty needs the more adjustment the longer recovery takes
<DocScrutinizer05>
might overshoot though
<DocScrutinizer05>
you could keep them outside the loops too
<DocScrutinizer05>
but ideally you find some sort of Euler, based on i counter in 22-25
<DocScrutinizer05>
the 22-25 loop will iterate the longer, the closer duty is to the target
<DocScrutinizer05>
so for higher i, the duty adjustment should be lower
<DocScrutinizer05>
duty++ and -- are really just meant symbolic
<wpwrak>
yeah, you'd probably want some t++ and then duty += f(t) or such
<DocScrutinizer05>
((will iterate the longer...)) when it iterates > NUM_SAMPLES times, duty is considered perfect
<DocScrutinizer05>
yes
<DocScrutinizer05>
oops is it t?
<DocScrutinizer05>
no it's i, line 21
<wpwrak>
t for the time you "correct"
<wpwrak>
a new variable
<DocScrutinizer05>
DANG!!!
<DocScrutinizer05>
25: until ((i++ > NUM_SAMPLES) or (abs(adc_t - adc_0) > NOISE_THRESHOLD))
<wpwrak>
since duty is measured in adc counts, while the correction loops count in loop counts
<wpwrak>
(i++) hehe :)
<DocScrutinizer05>
duty is measured in percent
<DocScrutinizer05>
line 6
<wpwrak>
i just used a float ;-)
<DocScrutinizer05>
you prolly want to make that ppm
<wpwrak>
polly some obscure implementation-dependent unit :)
<DocScrutinizer05>
nah, it's a plain simple integer, see line6
<DocScrutinizer05>
and line3
<DocScrutinizer05>
make line6 usleep(100000 - pw) or whatever you like
<DocScrutinizer05>
it determines range of duty and frequency of PWM
<wpwrak>
sure, in the end it's an integer. everything is :)
<DocScrutinizer05>
this one reasonably is a 12 to 16bit integrer, unsigned
<DocScrutinizer05>
it doesn't make sense to have it higher precision than your ADC can do and actually does
<DocScrutinizer05>
you also can't feed a real to usleep
<wpwrak>
i have my own timekeeping anyway. well, i do happen to have a function called usleep ...
<DocScrutinizer05>
usleep(MAXPWM) is the frequency (actually period) of your PWM signal
<DocScrutinizer05>
if you need higher resolution (higher MAXPWM) and same time higher PWM frequency, you should divide all parameters to usleep() by a constant factor
<wpwrak>
sure. but Vio_h(I very tiny) is Vcc is 3.3 V
<wpwrak>
else something is broken :)
<DocScrutinizer05>
for me INCREMENT is (NUM_SAMPLES - i)
<DocScrutinizer05>
for you it's SAMPLES - i
<DocScrutinizer05>
err
<DocScrutinizer05>
SAMPLES/i ?
<DocScrutinizer05>
a real 0<=duty<=1 is really messy to handle
<wpwrak>
i think one would want to calculate the quanta that went into or out of C1
<DocScrutinizer05>
duty +- i/SAMPLES, now that looks correct
<wpwrak>
probably more complicated. but i'm too lazy to do the math now :)
<DocScrutinizer05>
me too ;-)
<wpwrak>
and with a little luck there may be a simple direct temperature correction that works just as well, and we don't need all this ;-)
<DocScrutinizer05>
During all this, we read back Vc1 with the ADC (which is affected by leakage) AND COMPARE IT TO INITIALLY READ VALUE. If the values read back stay long enough AT INITIAL VALUE within the expected noise bounds, our duty cycle matches the correct Vc1 voltage
<wpwrak>
something like Ileak = 25 nA * max(1, tempC - 25) * (3.3 / 2 - real_Vc1); // or such
<wpwrak>
it's already posted :) let's see if anyone has questions
<DocScrutinizer05>
s/ For faster convergence, INCREMENT should be a function of the time it took to pull Vc1 back to the original value./ For faster convergence, INCREMENT should be a function of the time it took to pull Vc1 AWAY FROM THE original value./
<wpwrak>
that may be easier, indeed. i was thinking of some f(t, duty)