sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<sb0>
whitequark, ping
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<sb0>
I was surprised that my RLOC macro did the right thing in the device view, but of course: the bitstream is completely trashed, and nothing works when it is loaded into the actual device, even completely unrelated components
<sb0>
ah, vivado
<sb0>
sigh
<sb0>
that being said, fixing component placements and routes was a bigger trash fire in ISE
<davidc__>
what, you didn't like spending tons of quality time in floorplanner?
<sb0>
for routes you had to use fpga editor, which segfaulted every 15 minutes
<davidc__>
yeah, I never had to use FPGA editor - though it might have been easier.
<sb0>
the vivado interface for doing that is actually sane (though it would be better if the bitstreams didn't break, of course)
<davidc__>
I haven't had any major FPGA projects since Vivado came out, other than some zynq stuff (which reminds me, figuring out a sane migen integration for that is on my long term TODO list)
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<bb-m-labs>
build #2067 of artiq is complete: Failure [failed python_unittest_2] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2067 blamelist: Florent Kermarrec <florent@enjoy-digital.fr>
<hartytp>
sb0: need to double check I'm not doing something silly, but I still see timing issues with sayma_amc build
<hartytp>
CRITICAL WARNING: [Timing 38-322] The clock arriving at pin ISERDESE3/CLK must have the same master clock as the clock arriving at pin ISERDESE3/CLKDIV, and the latter can only be phase shifted by 0/90/180/270 degrees. Any auto-derived clock on pin ISERDESE3/INTERNAL_DIVCLK will be created with 0 phase. [/home/ion/scratch/tph/artiq/artiq_sayma/standalone/gateware/top.xdc:882]
<hartytp>
etc
<hartytp>
nope, never mind, python path issue was using an old version of misoc
<hartytp>
fixed
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<GitHub167>
[artiq] sbourdeauducq commented on issue #854: I gave it another try today, managed to ping the board with low packet loss rate after tuning the TX clock phase, but could not reproduce it after reloading bitstreams. https://github.com/m-labs/artiq/issues/854#issuecomment-366672542
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<GitHub157>
[artiq] enjoy-digital commented on issue #908: @hartytp: BTW for the test i'm asking, you just need to rebuild and flash the bootloader. I already had a case where disabling write_leveling was making things working. If this test make things working, then we could suspect something ont the write leveling sequence. If not, then we cannot say anything. https://github.com/m-labs/artiq/issues/908#issuecomment-3667065
<GitHub109>
[artiq] enjoy-digital commented on issue #908: @hartytp: BTW for the test i'm asking, you just need to rebuild and flash the bootloader. I already had a case where disabling write_leveling was making things working. If this test make things working, then we could suspect something on the write leveling sequence. If not, then we cannot say anything. https://github.com/m-labs/artiq/issues/908#issuecomment-36670658
<GitHub126>
[artiq] hartytp commented on issue #908: Hmmm...Normally, I've run `artiq_flash ... start` and then promptly run the openocd script to load the RTM gateware. That used to work fine. Now, I seem to have to run the openocd script after misoc boots or it prints `[ 0.028266s] INFO(board_artiq::serwb): waiting for AMC/RTM serwb bridge to be ready...` once and hangs there. After running the openocd script, it gets to
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<GitHub116>
[artiq] hartytp commented on issue #908: @enjoy-digital apologies, forgot to save changes. Hmmm...that was rebuilding with exactly the same code as this morning, but gave different results (no memory errors, but now freezes later on during boot). https://github.com/m-labs/artiq/issues/908#issuecomment-366736225
<GitHub11>
[artiq] hartytp commented on issue #908: Not sure if it's connected, but when I was playing around with the HMC830 I found that Sayma was prone to crashing. IIRC, I was checking to see if some part of the HMC830 startup process needed some time (e.g. after the power on reset) so I was adding delays followed by register dumps at various points in the initialization sequence. Some things I did would cause it to crash (a
<GitHub97>
[artiq] sbourdeauducq commented on issue #908: And how much noise do you have on the 1.8V rail? IME, I had more unexplained crashes before I added the capacitor on the 1.8V rail. Though unreliable SDRAM could cause those as well. https://github.com/m-labs/artiq/issues/908#issuecomment-366740427
<GitHub79>
[artiq] hartytp commented on issue #908: > And how much noise do you have on the 1.8V rail? IME, I had more unexplained crashes before I added the capacitor on the 1.8V rail. Though unreliable SDRAM could cause those as well.... https://github.com/m-labs/artiq/issues/908#issuecomment-366742634
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<GitHub99>
[artiq] hartytp commented on issue #908: hmmmm...running ``artiq_flash ... start`` a few times, I'm getting mainly memory errors, but sometimes I'm getting to "continuing to boot" before it crashes. ... https://github.com/m-labs/artiq/issues/908#issuecomment-366744884
<GitHub149>
[artiq] marmeladapk commented on issue #908: @enjoy-digital I commented out write leveling and I got warnings during compilation that this function is never used. However write leveling still shows up in boot messages (and memory check fails).... https://github.com/m-labs/artiq/issues/908#issuecomment-366756685
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