sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
[florian1 is now known as [florian]
[florian] has quit [Changing host]
[florian] has joined #m-labs
mumptai_ has joined #m-labs
sb0 has joined #m-labs
mumptai has quit [Ping timeout: 255 seconds]
rohitksingh_work has joined #m-labs
rohitksingh_work has quit [Ping timeout: 240 seconds]
key2 has quit [K-Lined]
gric has quit [K-Lined]
kristianpaul has quit [K-Lined]
kyak has quit [K-Lined]
zumbi has quit [K-Lined]
jaeckel has quit [K-Lined]
ysionnea1 has quit [K-Lined]
stekern has quit [K-Lined]
kaalia has quit [K-Lined]
[florian] has quit [K-Lined]
siruf has quit [K-Lined]
ohama has quit [K-Lined]
folkert has quit [K-Lined]
early has quit [K-Lined]
shenki_ has quit [K-Lined]
sandeepkr has quit [K-Lined]
cedric has quit [K-Lined]
ohsix has quit [K-Lined]
bb-m-labs has quit [K-Lined]
Ultrasauce has quit [K-Lined]
rjo has quit [K-Lined]
kuldeep has quit [K-Lined]
attie has quit [K-Lined]
acathla has quit [K-Lined]
wolfspraul has quit [K-Lined]
cr1901_modern has quit [K-Lined]
balrog has quit [K-Lined]
felix_ has quit [K-Lined]
larsc has quit [K-Lined]
bb-m-labs has joined #m-labs
folkert has joined #m-labs
mumptai_ has quit [K-Lined]
sb0 has quit [K-Lined]
ohsix has joined #m-labs
early has joined #m-labs
kaalia has joined #m-labs
cr1901_modern has joined #m-labs
Ultrasauce has joined #m-labs
cedric has joined #m-labs
jaeckel has joined #m-labs
cedric has quit [Changing host]
cedric has joined #m-labs
balrog has joined #m-labs
acathla has joined #m-labs
kuldeep has joined #m-labs
rjo has joined #m-labs
rjo has quit [Signing in (rjo)]
rjo has joined #m-labs
sandeepkr has joined #m-labs
rohitksingh_work has joined #m-labs
larsc has joined #m-labs
attie has joined #m-labs
kyak has joined #m-labs
kyak has joined #m-labs
<_florent_> sb0: I haven't made progress on the DAC clocking yet. I'll work on that but that would be good to synchronize with greg/joe since on my side I'm not able to observe the quality of the generated clock.
<_florent_> sb0: for the inconsitency on DDR input/out, that's probably due to copy/paste between projects and would have need a code review as you are actually doing
<_florent_> sb0: on the RGMII phy, the DCM is used for a 90°phase shift of the rx clk
sb0 has joined #m-labs
<sb0> _florent_, yes, but why is it needed? this looks like an ad-hoc fix for your board.
<sb0> _florent_, the clock is so bad that I think you should be able to observe the problem easily, no?
<sb0> _florent_, we can certainly capture the hmc830 output here
felix_ has joined #m-labs
wolfspraul has joined #m-labs
<_florent_> sb0: for RGMII, if phy/board is configured/designed to present a 90°phase shift clock to the FPGA, yes that's not needed. That was probably not the case for the board I tested and you are probably right, this should be an option.
<sb0> it should actually be moved out completely of the core and put in the platform file
<_florent_> sb0: thanks if you can capture the hmc830 output
<_florent_> sb0: yes probably
<sb0> e.g. patch the pins object to shift the clock
<sb0> aren't most synchronous systems designed so that you can, in most cases assuming reasonable pcb/chip characteristics, put a FF directly on the provided clock sampling the provided data?
<_florent_> sb0: is it on a spartan6 or an artix7 you want to have rgmii?
<sb0> kintex ultrascale
<sb0> it's for the sayma board
<sb0> i've already rewritten the phy to use DDRInput/DROutput and removed the clock chip
<sb0> but haven't tested anything yet
<_florent_> sb0: ok
<sb0> *the clock shift
<sb0> do you still need that pll?
<sb0> Greg has a design with the ddr ios directly clocked that works on sayma
<sb0> I think you definitely do not need pll + idelay at the same time ...
<_florent_> that's similar to what we just discussed and should probably moved outside
key2 has joined #m-labs
rohitksingh_work has quit [Read error: Connection reset by peer]
rohitksingh has joined #m-labs
sb0 has quit [Quit: Leaving]
sb0 has joined #m-labs
<sb0> _florent_, do you have bitfiles and all that is required to reproduce the clock issue with minimal installation?
<sb0> is it still ~rx_ctl & rx_ctl_d?
<GitHub139> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v7pmb
<GitHub139> migen/master ae063b2 Sebastien Bourdeauducq: sayma_amc: add Ethernet pins
<bb-m-labs> build #168 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/168
<GitHub100> [misoc] sbourdeauducq pushed 3 new commits to master: https://git.io/v7pOJ
<GitHub100> misoc/master 9106659 Sebastien Bourdeauducq: sayma_amc: introduce Ethernet support
<GitHub100> misoc/master 6633ae3 Sebastien Bourdeauducq: liteeth: fix RGMII PHY and make it platform independent
<GitHub100> misoc/master b51d7a2 Sebastien Bourdeauducq: Revert "liteeth: remove ad-hoc clk_freq parameter"...
<bb-m-labs> build #230 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/230 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
rohitksingh has quit [Quit: Leaving.]
<GitHub193> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/v7p3Z
<GitHub193> misoc/master cd9c4d3 Sebastien Bourdeauducq: sayma_amc: increase integrated ROM size, use default SRAM size
<bb-m-labs> build #231 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/231 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<GitHub161> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v7p3r
<GitHub161> migen/master f7816e4 Sebastien Bourdeauducq: sayma_amc: add Ethernet clock constraints
<bb-m-labs> build #169 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/169
<GitHub139> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v7pGL
<GitHub139> migen/master b0470e9 Sebastien Bourdeauducq: xilinx: work around Ultrascale DDR register default parameter idiocy
<bb-m-labs> build #170 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/170
<GitHub191> [migen] sbourdeauducq pushed 2 new commits to master: https://git.io/v7pZy
<GitHub191> migen/master 714c79e Sebastien Bourdeauducq: xilinx: use correct DDR register on KU
<GitHub191> migen/master 5638093 Sebastien Bourdeauducq: Revert "xilinx: work around Ultrascale DDR register default parameter idiocy"...
<bb-m-labs> build #171 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/171
<GitHub93> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/v7pc2
<GitHub93> migen/master ddf5281 Sebastien Bourdeauducq: xilinx: fix Ultrascale IDDRE1 pin names
<bb-m-labs> build #172 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/172
sb0 has quit [Quit: Leaving]
acathla has quit [Changing host]
acathla has joined #m-labs
sb0 has joined #m-labs
<GitHub109> [misoc] sbourdeauducq pushed 1 new commit to master: https://git.io/v7poM
<GitHub109> misoc/master 3ada03f Sebastien Bourdeauducq: sayma_amc: make vivado timing analyzer happy
<bb-m-labs> build #232 of misoc is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/misoc/builds/232 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
sb0 has quit [Quit: Leaving]
mumptai has joined #m-labs
siruf has joined #m-labs
ysionneau has joined #m-labs