12:58 <sb0> we don't have LEDs to blink on sayma/metlino? other than the SFP ones

14:20 <GitHub157> [migen] sbourdeauducq pushed 2 new commits to master: https://git.io/vyoiV

14:20 <GitHub157> migen/master 953e3f0 Sebastien Bourdeauducq: introduce platform files for Sinara

14:20 <GitHub157> migen/master c0025e4 Sebastien Bourdeauducq: fix permissions

14:23 <bb-m-labs> build #135 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/135

14:25 <GitHub49> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vyoii

14:25 <GitHub49> migen/master 42e73fd Sebastien Bourdeauducq: sinara: fix fpga id string

14:27 <bb-m-labs> build #136 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/136

14:39 <sb0> Joe's latest invention is "1V8 LCDS"

14:39 <sb0> sigh

14:39 <sb0> (LVDS)

14:40 <sb0> and I have no idea where 1V8 comes from

15:28 <hartytp> sb0: "LCDS" typo was probably my fault, will fix

15:29 <hartytp> 1V8 coppied from current 3U_VHDCI_Baseboard pdf

15:36 <sb0> hartytp, from that note at the bottom left? well there is no such thing as "1.8V LVDS", it's just "LVDS"

15:37 <sb0> there are different I/O standards for FPGAs (LVDS_18, LVDS_25) but all it does is configure the IOB properly so it outputs standard LVDS for the given bank power supply voltage

15:38 <sb0> you can plug a LVDS_18 into a LVDS_25, etc.

15:39 <hartytp> sb0: sure

15:40 <hartytp> I threw that page together really quickly by copying and pasting from a few places, without doing any real editing

15:40 <hartytp> It’s only supposed to be a template/placeholder until something proper is written

15:40 <hartytp> anyway, edited