<GitHub>
[artiq] cjbe commented on issue #670: @jordens the only thing pulling in m-labs/pyqt5 now is quamash: the recipe is fixed, but the conda package at m-labs/main has not been rebuilt with this new recipe (current build is 2016-12-01) - could you trigger a rebuild? https://github.com/m-labs/artiq/issues/670#issuecomment-283843885
<sb0>
did you align the start of the dma buffer to a sdram word?
<whitequark>
oh, hm
<whitequark>
what's an SDRAM word?
<sb0>
512 bits
<whitequark>
so 64 bytes?
<sb0>
same alignment requirement as the analyzer
<sb0>
yes
<whitequark>
oh.
<whitequark>
well that explains it
<whitequark>
also, that's a really obnoxious requirement
<whitequark>
there's no way to allocate 64-byte-aligned buffers currently
<sb0>
realigning stuff in gateware isn't exactly non-obnoxious either
<whitequark>
yes, but you only have to do that once
<sb0>
maybe you can allocate an extra 63 bits, look at the start address that you got, and pad the beginning with dummy data?
<sb0>
*63 bytes
<sb0>
that's *a lot* easier to debug than gateware realignment
<whitequark>
yes, that's really my only choice here
<whitequark>
well, it doesn't have to be 63, sec
<sb0>
better than spending a week on fixing obscure gateware bugs in the realignment logic
<sb0>
also, why is it that rust, a "systems language", cannot align things in memory? alignment requirements are pretty common when dealing with hardware
<whitequark>
you can't do that in C any better either?
<sb0>
there's posix_memalign. but C doesn't really have memory management...
<whitequark>
sure it does, malloc is in the C standard
<whitequark>
rust provides __rust_allocate, which takes an alignment argument (and which is not implemented in liballoc_artiq anyway), and its collections will generally ensure the elements are aligned
<whitequark>
and there's an (unstable) global attribute, which is equivalent to C's implementation-specific ones
<cr1901_modern>
Rust has an attribute for packed I believe (idk if it's stable tho)
<whitequark>
so their story here is similar, and also unsatisfyingly weak
<whitequark>
actually, most "systems" languages are pretty bad at interfacing with hardware
<sb0>
you call malloc() memory management? :)
<whitequark>
yes, malloc() is memory management
<whitequark>
no systems language I know of provides a decent interface for hardware registers, for example, or DMA
<whitequark>
well, that's not quite it
<whitequark>
there is an obscure Haskell dialect that is somewhat decent
<whitequark>
well, it has first-class support for bit manipulation and raw memory areas
<whitequark>
so you can describe something (I think they use PCI config space as an example in the report) and the compiler will guarantee that the code you write using those definitions conforms to (certain) hardware's expectations
<cr1901_modern>
By first class bit manipulation you mean "I can masking ops as objects to be assigned to a variable"?
<whitequark>
no
<whitequark>
I'm unconcerned with syntax
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<whitequark>
see section 3.6.8
<cr1901_modern>
ack
<cr1901_modern>
In any case, I think Ada also lets you create type safe device drivers, but I have no experience w/ this
<whitequark>
which assignment anyway, it's monadic
<whitequark>
though strict
<whitequark>
yes. I don't know Ada
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<whitequark>
cp: cannot stat '/var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/envs/_build:/lib/libcrypto.so.1.0.0': No such file or directory
<whitequark>
mv: cannot stat '/var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/envs/_build/lib/libcrypto.so.1.0.0-tmp': No such file or directory
<whitequark>
wtf
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<whitequark>
sb0: no, it still hangs
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<larsc>
sb0: which converter do you want to use with those lanes?
<sb0>
AD9154
<sb0>
yea it's 10, for some reason I had 12 in mind
<larsc>
AD9154 can do up to 12.5Gbps, but if your max data output rate is 1GSPS you only need 10Gbps
<larsc>
ah know, mistake in my document. 10.96 Gbps is max
<rjo>
sb0: i'll bring it up.
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<GitHub>
[artiq] cjbe commented on issue #670: @sbourdeauducq I see - thanks for fixing that build. There now seems to be a working quamash (0.5.5-py_2) in m-labs/dev, but m-labs/main still has 0.5.5-py_1. Is it possible to update the main as well? https://github.com/m-labs/artiq/issues/670#issuecomment-284100936
<GitHub>
[artiq] cjbe commented on issue #670: @sbourdeauducq the documentation relating to 3f556a3 / #361 ? I have not been able to reproduce this on Ubuntu - perhaps @r-srinivas may be able to reproduce? https://github.com/m-labs/artiq/issues/670#issuecomment-284101834
<whitequark>
sb0: it doesn't matter if they're LE or BE, because no data is shown as submitted