sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
rohitksingh has quit [Ping timeout: 240 seconds]
mumptai has quit [Quit: Verlassend]
rohitksingh has joined #m-labs
rohitksingh has quit [Quit: Leaving.]
<mithro>
sb0: is there something which explains how AutoCSR stuff works?
fengling has joined #m-labs
fengling has quit [Ping timeout: 256 seconds]
<cr1901_modern>
mithro: I seem to recall that SoC class uses introspection of CSR classes in order to figure out what registers to instantiate and when. You have to provide a few methods (I don't remember the names) so SoC can correctly figure out how to create these registers. >>
<cr1901_modern>
AutoCSR automates this by giving you some default methods so SoC finalization doesn't bitch
<cr1901_modern>
It's been a while since I used AutoCSR/Register Banks; I wanted to connect them to a little endian softcore, but sb0 didn't want me to add that feature
<sb0>
you softcore was 8-bit and endianness made no sense
<cr1901_modern>
right, can we omit that little detail please :P?
<cr1901_modern>
(the endianness only makes sense for procedure calls and stack-relative stuff. Neither of which should PROBABLY be writing to I/O)
fengling has joined #m-labs
<sb0>
whitequark, i don't see any use cases for exception-aware context managers on device. change __exit__ so it doesn't take any parameter?
<mithro>
What I don't quite understand is, If I want to take an action based on a read/write from a register - How do I do it?
<sb0>
cr1901_modern, writing BE CSRs on your system is trivial. supporting LE mappings in misoc is code that sticks around, increases LOC, decreases maintainability, may suffer bitrot, etc.
<sb0>
just because it can be done doesn't mean it should
<sb0>
mithro, use Csr.re signal
<sb0>
look at eg the w1c flags in rtio for an example
<mithro>
sb0: I assume that size/reset for CSRStorage are equivalent to size/reset of Signal - I'm not sure what atomic_write/write_from_dev/alignment_bits do? -- What do the re/we Signals inside the CSRStorage do?
<sb0>
well not strictly w1c, but similar, write anything to register to clear
<mithro>
I can't find anything called rtio in the misoc repo?
<sb0>
re is pulsed when the cpu writes to you
<sb0>
it's in artiq
<sb0>
mithro, if i answer all your questions above, will you write a nicely formatted doc about it?
<mithro>
sb0: you mean add a docstring to CSRStorage? If so - then yes - but I'm happy to try and figure it out from rtio first
<mithro>
sb0: It seems that CSRStatus is used for going Device->CPU and CSRStorage for going from CPU->Device?
fengling has quit [Ping timeout: 256 seconds]
<sb0>
CSRStorage can go both ways if you enable write_for_dev, otherwise correct
<cr1901_modern>
sb0: I DO appreciate that. Code that's not there can't fail.
fengling has joined #m-labs
<cr1901_modern>
I could write my own adapter or barrel-shifter anyway between CSR bus and CPU if I absolutely needed to use MiSoC w/ LE softcore
<mithro>
sb0: you use sphinx for documentation right?
<sb0>
yes
<sb0>
cr1901_modern, your cpu would use 8-bit writes
<sb0>
we even use 8-bit writes on csr with or1k
<mithro>
sb0: I still don't understand alignment_bits - It seems to add a bunch of lower bits into the register - Why is that useful?
<sb0>
eg if you have an address in 32-bit words in your migen design and want to expose bytes to the cpu
<mithro>
sb0: so it's just so you don't need to use slicing in the thing which contains the CSR?
<sb0>
yes and the alignment bits are stuck at zero, which helps (a bit) during debug
<mithro>
sb0: so, there is a re, r and w signals - I assume r and w are read/write - re is read enable?
<mithro>
sb0: I also don't quite get atomic_write - It seems to create a shadow register
<mithro>
sb0: Is this for when the CSR is bigger then the bus width?
<sb0>
yes
<mithro>
sb0: and it assumes writing to the lowest byte causes the write
fengling has quit [Ping timeout: 256 seconds]
<sb0>
correct
sb0 has quit [Quit: Leaving]
fengling has joined #m-labs
fengling has quit [Ping timeout: 256 seconds]
fengling has joined #m-labs
sb0 has joined #m-labs
<whitequark>
sb0: I think I'll just make __exit__ always receive None, None, None
<whitequark>
the field which holds the mapping to the host object
rohitksingh has joined #m-labs
fengling has joined #m-labs
fengling has quit [Ping timeout: 256 seconds]
<GitHub89>
[pythonparser] whitequark pushed 1 new commit to master: http://git.io/vuZEe
<GitHub89>
pythonparser/master 8bdc7ba whitequark: diagnostic.Engine: rename print_diagnostic→render_diagnostic; always call it.
<GitHub151>
[artiq] whitequark pushed 3 new commits to master: http://git.io/vuZgZ
<GitHub151>
artiq/master 03dd1c3 whitequark: Refactor the logic of printing diagnostics to solely rely on Engine.
<GitHub151>
artiq/master 5baf18b whitequark: transforms.inferencer: factor out _unify_attribute.
<GitHub151>
artiq/master 05fa808 whitequark: transforms.inferencer: make sure parallel/sequential is lone manager.
fengling has joined #m-labs
<whitequark>
sb0: does a method def __enter__(self): accept one argument or zero arguments?
<whitequark>
I mean, you call it as __enter__().
<sb0>
whitequark, ?
<whitequark>
I think my question was clear
<sb0>
well it works the same as other python methods, no?
<whitequark>
sure
<whitequark>
so is a method with only self argument nullary or unary?
<sb0>
unary until bound, obviously
<sb0>
are you saying my compiler didn't bind self? that's possible. i only developed this context manager stuff for specific purposes that did not need it.
<whitequark>
no
<whitequark>
I don't know how to best write the diagnostic
<whitequark>
if the __enter__ or __exit__ method has a wrong amount of arguments, should it say that it should have one, or zero?
<whitequark>
(four, or three?)
<sb0>
I'd be consistent with cpython
<whitequark>
cpython does not have a type system, it complains at runtime
<whitequark>
hm, I guess cpython thinks that it's one and four