03:36 <sb0> cr1901_modern, can you file the migen issues you had?

03:36 <sb0> with namer and that other thing

04:19 <cr1901_modern> (ClockDomain)Namer, yes, working on it now... "that other thing," I forget to what you refer :(

04:20 <cr1901_modern> If it's in reference to identifiers being decorated with __main__, I think I concluded that it's "not a bug"; just "unfortunate" :P

04:22 <sb0> yes, that one

04:22 <sb0> well, report it

04:22 <sb0> you eventually had written a good minimal program I think

04:24 <cr1901_modern> Yes, I think I found it- uploaded it as a gist.

04:25 <sb0> can you link it in a migen issue?

04:28 <cr1901_modern> Yes of course. I wanted to add a second example: neither renaming sys to new_clk_name nor new_clk_name to sys works.

04:30 <sb0> I'll have some time next month to look into migen/misoc so good to have a proper list of things to look into

04:30 <cr1901_modern> Sorry I keep breaking things (especially considering in 4 months I haven't actually come out with anything I feel worth publishing using Migen yet)

04:31 <cr1901_modern> Though that should change soon...

04:45 <cr1901_modern> sb0: https://github.com/m-labs/migen/issues/28 Working on the other one

04:47 <cr1901_modern> I updated the code example to create two simulations- one where the module's clock domain is renamed to sys, the other where the top_level's clock domain is renamed to a provided clock domain name

05:10 <cr1901_modern> sb0: https://github.com/m-labs/migen/issues/29

13:04 <ysionneau> the noarch stuff in conda does not seem very stable...

13:05 <ysionneau> https://github.com/conda/conda-build/issues/542 < ah, crap.

13:06 <ysionneau> this is why my test at having "artiq" be a noarch pkg failed over there: https://api.travis-ci.org/jobs/77123078/log.txt?deansi=true

13:07 <ysionneau> noarch means platform AND python version independant package ...

13:07 <ysionneau> that's obvious by its name, right...

13:08 <ysionneau> and that's not the first noarch issue I'm encountering

13:09 <ysionneau> https://github.com/conda/conda-build/issues?utf8=%E2%9C%93&q=is%3Aissue+is%3Aopen+noarch

13:10 <ysionneau> also I had to add this work around for noarch to even *begin* to build: https://github.com/fallen/artiq/commit/dc30ea3f9f7471b5a6f185b292c92f302598d97c ( https://github.com/conda/conda-build/issues/466 )

13:48 <tmbinc___> I'm trying to make xst infer an SRLC32E, which needs a reset-less shift register. What's the best way to remove reset from a particular Signal?

13:49 <tmbinc___> should i create a reset-less clock domain for the SRLC32E? Or is there some magic method to exclude a Signal() from being reset?

15:12 <ysionneau> sb0: under win64 with win32 pkg : I ran the unit tests, result is: http://pastebin.com/hzfStkVF

15:12 <ysionneau> that is with latest artiq conda package from anaconda.org

15:12 <ysionneau> (and the core device flashed accordingly)

15:48 <sb0> make_subprocess_transport raises NotImplementedError

15:49 <sb0> oh right, those tests need to switch event loops

15:50 <ysionneau> so the good news is we can definetely use those win32 packages for win64 =)

15:50 <sb0> ysionneau, bah. just looks like minor problems. do you have any trouble fixing those or what?

15:51 <ysionneau> I didn't try yet, I'm just reporting :)

15:52 <ysionneau> most of the things are passing

15:53 <sb0> and is that running in a VM on a 10-year-old computer or something?

15:53 <sb0> looks very slow from the core device tests that are failing

15:53 <ysionneau> yes it's running in a VM, which can explain the timings

15:55 <ysionneau> I get similar timings in a win32 VM

23:25 <GitHub101> [artiq] jboulder opened pull request #109: new ddb.pyon argument comment; use to put labels in GUI for TTL and DDS (master...master) http://git.io/vsdQP