sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<sb0> whitequark, can you hook up your code to the existing inline transform which solves this problem now in an acceptable way for the time being?
<sb0> this way we would have practical results sooner
<sb0> developing something better is planned for later.
<whitequark> sb0: I don't think that would be substantially faster than figuring how to fit your desired semantics instead
<whitequark> after all, I'm not necessarily saying this needs to be redesigned
<whitequark> it is entirely possible that interleaved inference/discovery is the right choice for ARTIQ
<whitequark> it's just that up to now, the compiler wasn't really done to cope with this.
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<cr1901_modern> whitequark: You don't mind that GNU /bin/true is 55 kilobytes, and yet you point out the verbosity of it's hello world package :P.
<whitequark> the size of /bin/true has no cost. the size of hello world package has substantial cognitive cost
<cr1901_modern> Point taken. Presumably it's an autoconf "tutorial" of sorts. And that by it's very nature is gonna suck
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<whitequark> sb0: ok, i figured out a way to do it. specifically, exploit the fact that you can effectively suspend and restart inference
<whitequark> so i would just gather more code every time i need to pull something in.
<sb0> yes, this is what the inline transform does
<sb0> with inspect.getsource
<whitequark> inline transform doesn't do inference
<sb0> also: we don't have to support object creation on the device. assuming the objects are already instantiated on the host when entering kernel mode is fine
<sb0> I was referring to your second sentence
<whitequark> object creation on the device is already supported anyways, for exceptions and range() and friends
<whitequark> and you have to put the object on the device somehow. what do you do if not create it
<sb0> the inline transform does name mangling to flatten the namespaces of multiple Python objects existing on the host
<sb0> if there is object/namespace support, you can use that maybe
<sb0> the only two things that we really need to support regarding objects is 1) a kernel calling a kernel in another object 2) kernels may modify attributes (of types supported by the compiler) of any object
<sb0> everything else is luxury and should *not* be a priority
<whitequark> the issue is that none of those things are hard.
<whitequark> they are either already implemented for other reasons or completely trivial to implement
<whitequark> the hard part is sane discovery and inference
<sb0> worst case, do it like the inline transform does, at the AST level and with name mangling
<sb0> this is proven to work
<sb0> and well, non-hard things, still take time when accumulated
<whitequark> the code for reading and setting attributes is already there
<whitequark> the code for calling a function is just reading an attribute and then calling it
<whitequark> i.e. also already there
<whitequark> assuming all the code is discovered, the only thing that has to be added is some form of user class type
<whitequark> (that would have the attributes to call)
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<GitHub114> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vOzUJ
<GitHub114> artiq/master 433cb94 Sebastien Bourdeauducq: doc: artiq git clone needs --recursive to fetch lwIP
<sb0> whitequark, are all your llvm patches merged upstream into openrisc?
<sb0> more funny stuff coming from clang...
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<travis-ci> m-labs/artiq#371 (master - 433cb94 : Sebastien Bourdeauducq): The build passed.
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<GitHub116> [misoc] enjoy-digital pushed 2 new commits to master: http://git.io/vOzzX
<GitHub116> misoc/master 52fba05 Florent Kermarrec: sdram/phy/initsequence: add burst chop 4 (BC4) for DDR3...
<GitHub116> misoc/master c03ef52 Florent Kermarrec: sdram/phy/s6ddrphy: add DDR3 support
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<sb0> mithro, this thing cannot compensate for clock/data skew variation after the initial calibration, can it?
<sb0> ah, it will, but with some data corruption
<sb0> even possibly large data corruption, as it may do a complete rescan of all idelays/bitslip possibilities if the skew has changed by over a nanosecond in the wrong direction ...
<mithro> sb0: It's just his initial version, I'm sure he'll improve it as time goes on
<sb0> thing is, I wonder if the 7-series hardware can support that
<sb0> at least without hacks such as reimplementing the SERDES in the fabric
<GitHub177> [artiq] sbourdeauducq pushed 1 new commit to master: http://git.io/vOgBa
<GitHub177> artiq/master 18f38e6 Sebastien Bourdeauducq: doc/manual: make sure correct Clang is used
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<travis-ci> m-labs/artiq#372 (master - 18f38e6 : Sebastien Bourdeauducq): The build passed.
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<GitHub35> [migen] sbourdeauducq pushed 1 new commit to master: http://git.io/vOgbm
<GitHub35> migen/master 9c902bc Ryan Verner: Port fpgalink_programmer to use newer fl library....
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<travis-ci> m-labs/migen#68 (master - 9c902bc : Ryan Verner): The build passed.
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<GitHub169> [artiq] whitequark pushed 1 new commit to master: http://git.io/vO2ac
<GitHub169> artiq/master d040224 whitequark: Update installation instructions.
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<travis-ci> m-labs/artiq#373 (master - d040224 : whitequark): The build passed.
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<cr1901_modern> sb0: Are you aware of any uses of Migen in a college class and/or digital logic 101 environment?
<sb0> nothing serious
<cr1901_modern> Maybe one day. Unfortunately, I'd suspect such a class would need to know Verilog simultaneously
<sb0> whitequark, there are still issues with llvmlite
<sb0> old patches still laying around artiq repos
<sb0> package renamed to llvmlite_artiq, compiler importing llvmlite_or1k
<sb0> conda scripts not up to date
<sb0> after the compiler imports llvmlite_or1k, travis will break
<sb0> (by default)
<sb0> er, llvmlite_artiq
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<cr1901_modern> sb0: How does one use ClockDomainsRenamer?
<cr1901_modern> nevermind, ignore... found it in decorators.py