<cr1901_modern>
Is it probable that if one wire on a bus attached to a flip flop is not kept in a stable state before latching, that it can affect the output of the flip flop on other bus lines?
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<GitHub121>
[artiq] fallen pushed 1 new commit to master: http://git.io/vsmsj
<GitHub121>
artiq/master da1398b Yann Sionneau: pxi6733: fix crash when samples are all the same...
<ysionneau>
sb0: Kathie confirmed the driver works for multiple simultaneous channels (with one clock)
<ysionneau>
now ARTIQ linux-32 packages are automatically generated also (and not just linux-64 via travis)
<ysionneau>
o_o, the travis build just restarted from scratch ...
<ysionneau>
sometimes travis has weird bugs
<GitHub65>
[artiq] fallen pushed 1 new commit to master: http://git.io/vsm08
<ysionneau>
hey mithro I can see you are contributing to the HDMI2USB project, are you guys aiming at using the misoc based firmware as the default one?
<mithro>
ysionneau: yes - I'm very interested in trying to revitalise the video part of misoc
<ysionneau>
very cool!
<mithro>
ysionneau: interested in helping out? :P
<mithro>
ysionneau: BTW Know anyone who was really interested in the original milkymist stuff? I'm very interested in getting people who were jazzed up about that hacking on stuff for our Numato Opsis board
<ysionneau>
by original you mean the Verilog SoC?
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<ysionneau>
18:57 < mithro> ysionneau: interested in helping out? :P < my time is very limited :x
<mithro>
ysionneau: more people interested in flickernoise and doing video manipulation stuff
<mumptai>
"$name has too many projects" -- would make a nice meme
<ysionneau>
so, you would like to port flickernoise on your HDMI2USB board?
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<cr1901_modern>
Finally figured out what was wrong with my design yesterday... not random register corruption thankfully :P. After every FPGA program cycle, my device needs to be reset, otherwise it locks up
<cr1901_modern>
I wonder what the best way to do this is Migen (i.e. a wishbone SYSCON module that resets for one clock)
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<cr1901_modern>
ysionneau: Have you ever dealt with an FPGA design "error" where DRC warns you that a signal "does not drive" any load, but it's routed anyway?
<mithro>
ysionneau: Yes, we would love to port flickernoise to the Numato Opsis board
<cr1901_modern>
So it appears I'm still wrong. Xilinx's compiler/PAR tool is actively ignoring initial values for my reset signal and always keeping it "1", unless I explicitly code it to be "0" in my FSM (active low)... wtf?
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<rjo>
sb0: does the idle experiment being started automatically rely on the tcp stack keepalive/idle exclusively? what happens if python hangs but the tcp stack is still alive?
<GitHub24>
[artiq] whitequark pushed 1 new commit to new-py2llvm: http://git.io/vssho
<GitHub24>
artiq/new-py2llvm 27a6979 whitequark: LLVMIRGenerator: use sret when returning large structures.