lekernel changed the topic of #m-labs to: Mixxeo, Migen, MiSoC & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<kristianpaul> haha
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<sb0> got the misoc bios to compile with gcc 4.8.2 (and that patch) :)
<sb0> idk if it works
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<bvernoux> hi
<bvernoux> for those interested in a nice FPGA board
<davidc__> bvernoux: what USB3 phy/transceiver are you using?
<bvernoux> it is the only one existing TI USB1310A
<bvernoux> no other exist in fact ...
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<davidc__> bvernoux: gotcha, just a PHY not a txcvr
<bvernoux> yes
<bvernoux> only PHY
<bvernoux> all other stuff are done in FPGA
<bvernoux> with an USB 3.0 Device stack written in Verilog
<mumptai> hi
<bvernoux> which should take less than 9Kcells
<bvernoux> anyway the USB 3.0 stack is not my work but Marshall Hecht's work
<mumptai> if there is a migen dev roadmap, is a vhdl export on it somewhere?
<bvernoux> Verilog is available here
<bvernoux> no there is not migen dev roadmap for it
<bvernoux> all is written from scratch in verilog
<bvernoux> and it is a huge work
<mumptai> i actually meant migen itself
<bvernoux> also USB 3.0 Device compliance test are pratically done
<bvernoux> missing feature are about power management
<bvernoux> and it will be only usb 3.0 device stack no host at all
<mumptai> but i can imagine that the protocol handling might be a bit tricky, does usb3 require downward compatibility of all all usb3 devices?
<bvernoux> yes it will support USB 2.0 too
<bvernoux> the USB 2.0 device was done before
<bvernoux> in respo there is both version
<mumptai> how fast can it actually go with a decent PC as host?
<bvernoux> IIRC it was > 200MB
<bvernoux> but was limited by the PC
<bvernoux> on FPGA side it shall go at maximum speed
<bvernoux> it is only limited by PC and USB 3.0 on host
<bvernoux> anyway the stack is not finished
<mumptai> and the fifo i/f is something like 32@100MHz ?
<bvernoux> phy pipe are 16bits
<bvernoux> 16*250Mhz IIRC
<mumptai> k ;)
<bvernoux> ij fact descrambling runs at only 125MHz
<bvernoux> but decoding 4 symbols at time
<bvernoux> so it work in parallell like if it will run at 500MHz
<bvernoux> which is very tricky on Cyclone4 ...
<bvernoux> 4 symbols = 128bits
<bvernoux> 128bits produce 32bits of data at end
<bvernoux> so 4Gigabits of data
<bvernoux> so a theorical maximum speed of 488MB/s
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<wpwrak> sb0: relocated to .hk, closer to the cornucopia of gadgets ? :)
<sb0> yes! =]
<wpwrak> wow. that came sudden. indefinite or just to visit for a while ?
<wpwrak> s/sudden/suddenly/ # headache vs. grammar, 1:0 :(
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