rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<apritzel> jernej: where do the values in this phy_init[] array come from? from a dump? b/c my PHY dump looks quite different in those registers
<apritzel> and did you read any values from the boot0 binary? the bit delay values, for instance? the delay values in my PHY dump look again quite different, but at least the structure and grouping look similar
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<jernej> apritzel: phy_init[] values are stored in 2d array at boot0 file offset 0x8764. I didn't figured out how correct values are selected, I just noticed that in my case they are first line from that 2d array.
<jernej> apritzel: I said that bit delay compensation values will be different for you, they are stored in tpr11 and tpr12, which differ between my box and your board
<jernej> I'll get OPi in a few days, then I'll be able to test there too
<jernej> apritzel: I'm looking at phy_init[] again and I'm pretty sure you should have same values as me, unless value at 0x3006200 is not 0x5000 - but that would suggest you don't have H616 but something similar (or different die revision)
<jernej> can you read out that location? can you give me your phy reg dump? first 4k is enough
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<bauen1> it also looks like for booting from nand the sbrom will first look for an image containing the magic strings "BT0.RRTB", "BT0.DMTB", "BT0.NTAB"
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<apritzel> bauen1: I don't think we have seen any actual devices with ARMv8 cores having NAND - (which is a good thing!)
<apritzel> jernej: readl 0x03006200 gives me 0x32c05000
<bauen1> are thesenice
<bauen1> *nice
<bauen1> just looking into it if there are maybe some bugs
<bauen1> but tbh, if i'm already gonna abuse the rtc and patch the sbrom i might as well copy / paste a few nops to reduce the attack surface
<jernej> apritzel: can you also post phy register dump?
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<jernej> apritzel: I don't see any difference in phy_init[] values, both dump and that register values are same as on my box
<jernej> and bit delay compensation values are all 7, which means it's not enabled
<apritzel> phy_init[]> this is probably because I need to clean my glasses, to not mix up 0x0c and 0xc0 ;-)
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<jernej> apritzel: so, any luck with DRAM?
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<bauen1> is it already black friday week or are the local retailers just starting early ?
<buZz> black friday is now a 2month long event
<buZz> soon it'll overtake the entire year
<bauen1> tbh i wouldn't mind that happening
<buZz> murderous rampage anyday you need to buy a bag of rice at the store
<bauen1> black friday sales probably run half of dn42 lol
<buZz> full on thunderdome battles for a bottle of orangejuice
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<apritzel> jernej: sorry, nothing yet. I reverted all my diagnostics and debug hacks, but same as in the beginning: all rank/width checks fall through, then it panics
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<apritzel> jernej: I get "write leveling finished|read calibration failed!"
<jernej> apritzel: try without read calibration...
<apritzel> yeah, was about to try that. I needed to disable all of read calibration, read training, write training, then it went through, but reported 128MB, and didn't return to FEL
<apritzel> will debug later tonight ...
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