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<smaeul>
apritzel: bauen1: I don't think 0x030000d0 does anything unless the fuse is set, so I don't think you can dump SBROM without it
<smaeul>
if you (or anybody with an H616 board) send me an NBROM dump (or a PR to sunxi-blobs), I could tell you where the CPU hotplug flag is
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<smaeul>
I actually used super-standby to first dump the SBROM. I could not get the CPU hotplug method to boot even hello world from wdreset
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<smaeul>
CPU hotplug is literally the first thing BROM checks, so it's before all of the silicon bug workarounds ;)
<smaeul>
apritzel: bauen1: indeed super standby requires an eGON image. it also must have a length aligned to 1k (which apparently is larger than normal boot)
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<apritzel>
smaeul: yeah, I tried 0x030000d0, and it did nothing: bit 31 sticks, but no change when reading from 0x0, and FEL keeps working (tested both from U-Boot and via FEL)
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<apritzel>
smaeul: your "literally the first thing BROM checks" tickled me, and you are right: the magic is the same as in the other SoCs, and needs to be in 0x070005c0, the address is then in 0x070005c4
<apritzel>
untested (getting late here)
<apritzel>
smaeul: will send you the dump anyway, for your collection ;-)
<smaeul>
awesome, thanks!
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<apritzel>
jernej: when you wake up: can you try " + 0x5c0" instead of " + 0x1b8" in the FEL64 patch, for the H616?
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<bauen1>
smaeul: probably because the hotplug method skips a few register writes related to clocks
<bauen1>
smaeul: but most importantly to SYS_CFG to enable all SRAM (and probably other components) (or maybe bring them "out of reset"
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<bauen1>
e.g. on the H6 SRAM A1 is enabled at reset but you need to work a little magic to enable e.g. SRAM A2
<jernej>
apritzel: 5c0 seems to work, but I get U-Boot header CRC mismatch for some reason
<jernej>
FEL still works though
<jernej>
MoeIcenowy: What's insane?
<jernej>
apritzel: if I enable FIT and SPL_LOAD_FIT in U-Boot, gcc reports overflow for 360 bytes :(
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<apritzel>
jernej: yes, U-Boot starts with this magic instruction word, that is both a branch in AArch32 and an almost-nop in AArch64. The next instruction is an AA64 branch, so you get a switch
<apritzel>
jernej: U-Boot header CRC mismatch> are you trying to boot the whole u-boot-sunxi-with-spl.bin image directly in sunxi-fel?
<apritzel>
jernej: the 64-bit SoCs use a FIT image, which is not (yet) supported by sunxi-tools
<apritzel>
jernej: I made some patches a while ago, need to revive them
<jernej>
apritzel: correct, but I haven't enable FIT yet
<jernej>
see my message about 360 bytes overflow
<apritzel>
right, saw this
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<apritzel>
I was wondering if we can cheat and ditch the whole AXP driver, instead just issue some I2C writes
<apritzel>
You just enable DCDC-D?
<jernej>
actually, it's already enabled, just set it to correct value
<jernej>
note, enabling I2C brings other dependencies - clock configuration (PRCM) and gpio configuration
<jernej>
apritzel: did you try to use my DRAM driver on OPi?
<apritzel>
no, not yet
<apritzel>
but will try it later today
<jernej>
apritzel: do you really think I2C driver is so big? AXP driver is already as small as possible
<jernej>
well, almost, but those calculations take only few instructions
<apritzel>
I don't know, just felt like a waste to have a "driver" at all for just a single register write
<jernej>
check axp305.c, you'll see it's pretty minimal
<apritzel>
jernej: actually: the H616 can boot >32KB eGON images
<apritzel>
jernej: for now you can try to remove the artificial limit check in the build system?
<apritzel>
(or relax it)
<jernej>
yes, I can - where is this check?
<apritzel>
jernej: don't know from the top of my head, there is at least one in mksunxiboot, and in another one somewhere
<apritzel>
try to chase down the error message
<jernej>
ah, it's from linker script...
<jernej>
found it - in sunxi-common.h
<jernej>
apritzel: I updated it to 48 KiB and it seems to work
<jernej>
however, then I have to boot U-Boot proper with second command over FEL
<jernej>
all in one doesn't work anymore
<jernej>
ah, it seems something else needs to be fixed in sunxi-fel, it complaints when using bigger SPL only
<jernej>
ok, I lifted limit in sunxi-fel and it works normally now
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<jernej>
apritzel: you need at least these changes for OPi DRAM: http://ix.io/2EVC if that doesn't work, probably ODT and maybe bit delay compensation settings need adjusting too
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<apritzel>
I should create a cron job for "git fetch jernej" ;-)
<jernej>
ah, sorry, it's early development...
<jernej>
I promise I won't push anything in near future
<jernej>
I think it's time to split patch and work on ATF
<jernej>
and Linux
<apritzel>
jernej: no, that's totally fine! No worries
<apritzel>
jernej: you are doing a great job on that
<apritzel>
TF-A is just a bit annoying, since this SRAM location is so baked in
<apritzel>
jernej: so about the AXP DRAM issue: in the past the PMICs were somewhat preconfigured to power DRAM out of reset, I wonder why this is not the case here?
<jernej>
it's powered, just not at appropriate voltage
<apritzel>
too low?
<jernej>
yes, but I forgot at how much
<apritzel>
because in the past we had 1.5V on LPDDR3, and that was at least working
<apritzel>
jernej: what are the DRAM chips on your TV boxes?
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<apritzel>
jernej: the OPi has two Samsung K4B4G1646E, 4Gb x 16
<jernej>
apritzel: 8x MT41K1G4RH
<jernej>
so each IC is 4 x 1 Gb
<apritzel>
so mctl_auto_detect_rank_width() falls through for me, but it should be 32bit, 1 rank
<apritzel>
but this might be a red herring, there might be something else wrong ...
<jernej>
did you apply my patch?
<apritzel>
yes
<apritzel>
are your chips DDR3L or DDR3?
<jernej>
ODT settings are also different
<jernej>
DDR3L
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<jernej>
what about frequency? did you adjust it?
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<apritzel>
no, boot0 uses 720 MHz, IIRC, you have 696, so that should fit? I can try to lower it, to get some wiggle room for the other parameters
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<apritzel>
jernej: scratching my head over the addrmap registers: the chips on the OPi-Zero2 have 15 rows, 10 columns (datasheet), and are organised as single rank, 2 x16 chips, that should give the actual 1GB, if my math is correct
<apritzel>
argh, nevermind, mixed rows and cols up in one register, so the boot0 dump matches what the SPL writes