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<pablet>
Hi everyone! I have a tiger-cdr board (V3S) with a spi NOR flash and I mounted a pin-compatible spi NAND flash on it. But now I cannot boot from it. I was trying to modify U-Boot, but I'm a bit lost at this point. Do I need to set all NAND-related config flags on the config file? or are these intended to handle a standard NAND flash?
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<dgp>
pablet: does the v3s bootrom support spi nand? I can't remember seeing that
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<pablet>
dgp: I am not sure, but I saw some boards mounting spi nand, so I guess it should be possible...
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* dgp
looking at the datasheet..
<dgp>
I'm working on a v3s board with spi nor at the moment :)
<dgp>
Does look like the bootrom supports booting from spi nand. My guess would be it's some uboot configuration thing or the SPL doesn't support spi nand at all yet
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<pablet>
I didn't try SPL, maybe I should
<dgp>
pablet: you need to have the SPL and then real uboot on the flash. At the right places
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<hitech95>
guys i have a question related on the problem I had yesterday. The A33/R16 have the external 32K clock output pin. This looks to be controlled by a gate in the RTC. I would like to know how i can enable/disable that gate. https://github.com/torvalds/linux/blob/master/drivers/rtc/rtc-sun6i.c#L256
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<wens>
from userspace? you can't.
<wens>
the common clock framework is only usable from kernel space
<hitech95>
wens, my idea was to create a dummy module to request the clock.
<KotCzarny>
what about devmem?
<hitech95>
That clock is used by a BT module. I triedto use the devmem2 to write to the right register but nothing happens.
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<KotCzarny>
you probably need to lax the kernel mem access for that tho
<hitech95>
KotCzarny, how?
<KotCzarny>
dont remember the option name, its in debug kernel config menu
<hitech95>
wens, I have the scope attached on that pin on the input of the AP6212 but even if i write that register nothing comes out. The external 32k osc is up and running (tried with a scope in the pins)
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<wens>
I assume you read back the register to check that the bit toggle worked?
<wens>
hitech95: aside, if you want the kernel to do everything for you, serdev and associated stuff is the way to go
<wens>
hitech95: but we had some trouble getting the btbcm driver to work properly :/
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<hitech95>
wens, do you have a reference or something? just to understand! Right now I would like to have a lock and a reset line working for the blootooth. than i will see how it works. (I'm still tring to understand how the wireless section works without having the wakeup signals managed in the driver (my DTS has no reference to those signals)
<MoeIcenowy>
mripard, wens: should I keep "allwinner,sun50i-a64-sram-controller" compatible in the sunxi_soc driver source code? (it's already there
<MoeIcenowy>
(and then add the "allwinner,sun50i-a64-system-controller" compatible and the !"syscon"
<hitech95>
MoeIcenowy, sorry for ping. You'r one of the developer of the audio codec on sunxi right? I asked lot's of times ago a an info and i'v been told thet only a couple of people knows how that work. Can I ask you a couple of questions? (In any case thanks for the great works)
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<MoeIcenowy>
hitech95: you can ask although I cannot guarrantee to be able to answer...
<MoeIcenowy>
I don't know it well either
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<hitech95>
MoeIcenowy, oh thx. I try to ask. I have a A33/R16 board. Alsa sees the codec but for some odd reason also the mics and line in are in the playback side. I read the user manual of the soc and I got more confused. To mee looks like that the codec can treat all the input and mix it toghether via some mux/amplifiers. So for example to have a loopback. I think that there should be a way to turn the microphones and line input to the recording side. I
<MoeIcenowy>
he just wants the AXP80x patches are present ASAP
<MoeIcenowy>
(and make it a requirment of the MMC patchset
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<wens>
sounds like I need to get things going
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<hitech95>
wens, can I ask you some more informations about the serdev and Bt problems you told me before?
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<wens>
hitech95: ask mripard, he did the tests, and might still have a wip branch around
<hitech95>
wens, ok. He is in my timezone. Perfect. I'll try ti ping him later or tomorrow.
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<hitech95>
wens, according to a old irc log I have seen that also mripard had problems related to BT with my same board (bpi m2m). He was working with MoeIcenowy.
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<jernej>
but since I wasn't paying much of attention about that, I might be wrong
<MoeIcenowy>
jernej: have you find the corresponding MMIO area for the DE2 SRAM?
<MoeIcenowy>
on H6
<jernej>
you mean for sram controller?
<MoeIcenowy>
yes
<MoeIcenowy>
currently all SRAM areas are MMIOed
<MoeIcenowy>
when controlled by sunxi_sram
<hitech95>
jernej, yup i have seen that commit. Right now i'm having problems on generating the 32k clock for the bt module. I'm tring to understand how the linux firmware interface work to load the blob from userspace. than i'll try to us ethe same driver used by the rpi (hoping for a working BT)
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<jernej>
MoeIcenowy: H6 needs exactly the same bit at the register located on the same address as A64 to be enabled in order to access DE3 MMIO
<MoeIcenowy>
yes, but where's the SRAM controlled by the bit?
<jernej>
you mean in my code?
<MoeIcenowy>
no
<MoeIcenowy>
on hardware
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<jernej>
ah, you mean where is the memory location of SRAM region shared by DE3, if it is set to be accessed by CPU instead of DE3?
<jernej>
I never checked
<jernej>
Isn't that just SRAM C as stated in H6 memory map?