ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion | IRC log http://irclog.whitequark.org/linux-rockchip | Community GH https://github.com/linux-rockchip | Rockchip GH https://github.com/rockchip-linux | ML https://groups.google.com/group/linux-rockchip
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<wzyy2> I think it's a pcie driver issue, not dts issue.
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<Pix> rtp, no, i'm no developper, so i used my money and bought an usb-powered 5400rpm fan that i screwed on the rad
<beeble> looks like this 2pin header next to the maskrom button has only a power supply when used with a excavator
<Pix> aah
<Pix> ok
<Pix> well, another option is to replace it with a 5V fan and plug the fan on the 5V of the 40-pin gpio connector
<Pix> :p
<Pix> (but no control over it)
<rtp> beeble: oh, thanks for the info. I've started looking at the schematics yesterday and got same feeling, but I was unsure if I read them right
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<beeble> Pix: if you take a 5v pwm fan then you can control it
<rtp> Pix: I'm not convinced the fan is really useful btw. I compiled a kernel on my sapphire with a "quite" big kernel config. I took 1h and the temperature did not reach more than 70C according to the thermal zone
<Pix> gab, looks like the original fan will never power up, do like me!
<Pix> gab and i are trying some cpu mining on it
<Pix> and it hits ~80
<Pix> with the "usb fan" i plugged, it stays at around 55°C
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<gab> rtp: there's a signal called "Motor_PWR" described on page 20 of the schematic, do you think that would be it ?
<rtp> gab: I was more wondering about vcc_chareg (and vcc_chareg_en)
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<gab> sounds like a typo with "charge" ;p
<gab> (what could chared mean otherwise ?)
<gab> seems to be linked to usb-c
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<gab> btw, if there something in sysfs or elsewhere to control the gpio pins ?
<gab> hmm... ok, you mean VCC_CHAREG comes out of pin 44 of the MXM header linked to exctavator ?
<rtp> for gpio, you have /sys/class/gpio stuff. Use echo "999" > export and then you have a gpio999 directory to play with. There's also a /dev interface iirc
<gab> ok
<rtp> yeah, that's what I meant. it seems to me that VCC_CHAREG comes only from the excavator
<gab> hm :(
<rtp> It was late when I've looked at it yesterday so it was nice to read early that I was not the only one making this conclusion
<gab> I don't see why it couldn't be powered directly by the sapphires 12V input
<gab> that's not such a huge fan
<gab> maybe it'd be worth it to ask someone at varms to confirm it
<gab> Pix sent them some questions earlier and they seem to be answering quickly
<rtp> imho, dont try to understand too much what the hardware guys did. When you look at the recovery key which is connected to an ADC, you understand that they may be "creative"
<gab> yeah, I already worked with hardware ppl :)
<rtp> oh, nice. maybe asking them their schematics would be nice. at least to make sure it's really the same thing as the one from the rockchip wiki
<beeble> hey, don't blame us hardware guys for everything :)
<gab> I think the schematics I have came from the varms site
<gab> beeble: well, more than once I found myself wishing to try the same drug they used ;)
<gab> but the same applies to software guys I worked with :p
<gab> some are just less rational than others
<rtp> beeble: I did not say that software guys were never to blame :)
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<rtp> gab: if you happen to have the link for the schematics on vams website, please share
<rtp> damn. how could I have missed that ? :( thanks
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<gab> hm... I'm wondering if the DDR can be overclocked on the sapphire board
<beeble> there is little to no perfomance gain in going from 1600 to 1866 if you have pure cpu workload
<gab> well actually that's some memory intensive workload
<gab> the kind that gains a lot by using hugepages instead of "normal" virtual memory
<gab> do you know how to test that ? (guess it needs some change in uboot or the device tree ?)
<beeble> with cpu workload i mean you are only running the cpu cores and not any other memory using peripherals (graphics etc)
<beeble> you have to change the ram timings in u-boot (via dts)
<gab> hm for the moment that's pure cpu, but it does lots of random access over large ranges of memory, so memory latency is a critical parameter
<gab> btw I plan to use opencl on the mali later
<beeble> for now it's still a register dump of the ram controller. jedec timing based one is incoming but will most likely miss 2018.03
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<gab> great, thanks for the info
<beeble> gab: look at rk3399-*ddr3-*.dtsi in arch/arm/dts in u-boot (mainline)
<beeble> with the miniloader you are out of luck :)
<gab> I'm not using miniloader
<gab> nice, thanks a lot :)
<gab> I'll try to fiddle with that
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