<naobsd>
and probably mask rom does something after return to lr, it seems rkflashtool complete usb transfer
<naobsd>
I have no idea what condition is expected at return :(
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<rperier>
hi all
<rperier>
did someone try u-boot on veyron ?
<rperier>
(upstream of course)
<lautriv_>
bashintosh, got some results on 5.1 ?
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<sjoerd>
mmind00: thanks for the detailed review
<mmind00>
sjoerd: that's one of the points the whole Rockchip work taught me ... spotting things :-)
<sjoerd>
yeah
<sjoerd>
you also spotted some things i simply copied from other boards (like the emmc pwr pin handling), which is nice
<sjoerd>
should probably fix the other ones as well i uess
<mmind00>
sjoerd: possibly ... I think the mmc power sequences are still quite new ... veyron were the first to use them here ... also nice for stuff like special regulator pins of wifi chips
<sjoerd>
Nod
<sjoerd>
these boards don't striclty need the emmc one as far as i can tell, it's an issue on the Exynos Odroid XU3 where the rom doesn't properly reset the emmc and then fails to boot from it
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<mmind00>
sjoerd: yep ... but I hate hunting for pins, so having everything described is quite nice too
<sjoerd>
Oh don't get me wrong, i fully agree with you
<sjoerd>
just saying that not having it does't cause practical issues on the rockchip boards it seems
<sjoerd>
mmind00: do you have a preference for the order of rockchip.txt ?
<sjoerd>
*order in
<mmind00>
sjoerd: for new stuff, I'm hoping on alphabetically :-)
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<sjoerd>
Will do :)
<sjoerd>
It's seems somewhat unsorted atm, so i wanted to double-check ;)
<mmind00>
sjoerd: the veyron boards + the rk3368 one are sorted though ;-)
<mmind00>
someone could sort the others too :-)
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<sjoerd>
heh
<sjoerd>
maybe as a seperate patch :)
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<mmind00>
sjoerd: for the time being, I guess it should just sit below the rock1
<sjoerd>
that's where i just put it
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<sjoerd>
mmind00: hrmng, trying to use mmc pwrseq seems to result in the emmc not working (weirdness)
<sjoerd>
mmind00: any idea what the emmc_pwren actually does?
<mmind00>
sjoerd: setting the reset gpio to 1 and then 0 ... (or 0->1 depending GPIO_ACTIVE_* setting)
<sjoerd>
mmind00: not that one
<sjoerd>
the function on the pin
<mmind00>
sjoerd: yeah, just saw
<mmind00>
sjoerd: according to the schematics it actually _does_ lead to the reset pin on "INAND"
<sjoerd>
so, oddly, changing the function to gpio & doing the emmc reset using the standard sequence seems to fail
<sjoerd>
mmind00: indeed
<sjoerd>
mmind00: So it is the right pin and you should be able to do the emmc reset sequency on it
<mmind00>
sjoerd: is the GPIO_ACTIVE_* setting right in the dts?
<sjoerd>
Yup and tried both variations to double check as well
<sjoerd>
Next step is to see if i can poke the pin with a multimeter to see if it behaves as i think it does
<sjoerd>
(but that's for tomorrow)
<sjoerd>
(i really need to buy a scope at some point)
<mmind00>
sjoerd: ok ... if it really doesn't want to work ... the emmc-pwrseq is definitly not mandatory :-)
<sjoerd>
mmind00: what i do wonder is what the gpio3b1 pin function called emmc_pwren does ? (Wonder if that cause the soc to perform the reset sequence or somesuch)
<sjoerd>
mmind00: sure, I just hate when something i think should work doesn't :)
<mmind00>
sjoerd: yeah ... same for the sdmmc_pwren ... which normally just gets wired to a fixed-regulator
<mmind00>
sjoerd: :-D
<mmind00>
I know that feeling ... have this with the rk3188 uboot for the last days
<sjoerd>
:/
<sjoerd>
no joy thusfar?
<mmind00>
sadly nope, and I lack uboot experience to actually know what I'm doing ... but looks like Simon wants to play too
<sjoerd>
Simon wanting to help out is a good sign
<sjoerd>
annoyingly it's one of those things where if you get one of the details wrong you get no feedback at all :/
<mmind00>
sjoerd: yep
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<sjoerd>
here the soc also has an emmc_rstnout pin but that's not connected
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<sjoerd>
Right re-reading the jedec standard, after powering up the emmc, it's expected for the reset line to be low for at least 1us, then go high at which point it should start resetting and be ready for commands in 200us..
<sjoerd>
which i guess means the pwren line just pull that pin up once you init the emmc causing the same effect or somesuch
<sjoerd>
guess my multimeter should show if the pin stays correctly high
<sjoerd>
and with that ramble, it's time got get sime sleep
<mmind00>
sjoerd: gn8 then :-)
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<bashintosh>
akaizen: Yes there is a Rockchip 5.1 SDK but it's not free and behind NDA >_>
<akaizen>
bashintosh: direct from RK?
<bashintosh>
yes from RK direct
<akaizen>
bashintosh: I know of hw manufacturers' 5.1 sdk which seem to be derived from RK source and then make their own improvements
<akaizen>
bashintosh: do you have someone you could put me in touch with?
<bashintosh>
akaizen: with RK R&D you mean?
<akaizen>
Yea, the guy I know i eng side so not sure if its the 'proper' way to go
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<bashintosh>
akaizen: check you pvt messages ;)
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