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<whitequark>
ARGH
<whitequark>
the busses in hamburg have no concept of route, I swear
<whitequark>
there are two stops for the same bus number near my hotel, and they go at least three different routes from there, dependent on, including but not limited to, odd/even, day of week and phase of moon
<whitequark>
I can't *read* the timetable, but the complexity in it rivals the diagrams in the x86 ISA manual
* whitequark
is now... somewhere in hamburg.
<whitequark>
well, at least hvv.de has a really amazing route planner
<whitequark>
DocScrutinizer05: and you can actually use yosys+abc+qflow as a fully FOSS ASIC toolchain
<whitequark>
no fpga though yet
<whitequark>
but if someone implements PAR and bitstream gen, it's possible to actually generate the bitstream on an FPGA reconfugirung itself
<DocScrutinizer05>
errr, too much info
<DocScrutinizer05>
on a sidenote: I checked flights and railway Nue->HH->Nue a few days ago. Seems the only(!) difference is: flights go only 2 times a day, but are only 70 minutes
<DocScrutinizer05>
while train costs almost same but takes 7+h
<DocScrutinizer05>
now if you could smoke in train, I'd still ponder. But a 7h no-smoking vs 70min, that's a clear nobrainer.
<DocScrutinizer05>
anyway, obsolete topic, today
<whitequark>
yeah, I'm out in less than 24h
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<larsc>
train nue->hh is less than 6h
<larsc>
normally
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<whitequark>
I have four hours tomorrow to look at something in Hamburg
<whitequark>
ideas?
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<apelete>
larsc: I've been playing with preparing next data while dma is transfering current data
<apelete>
wrote a first version where I had jz4740_pre_request() and jz4740_post_request() callbacks, with jz4740_pre_request() relying on jz4740_pre_dma_transfer() function which only do dma_map_sg() while dma is trasnfering data
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<apelete>
didn't noticed any improvement so I tried doing dma_map_sg() + dmaengine_slave_config() + dmaengine_prep_slave_sg() all together in parallel
<apelete>
that last combination doesn't work yet, here's the patch I'm working on if you care to take a look;