Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<pietrushnic> Is there anyone who successfully built LiveSuit image for A20 (Cubietruck) ? I tried sunxi-bsp and it looks like it lack a20 eFex,eGon and wboot.
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<nahom> NiteHawk: Hello!!
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<NiteHawk> hi nahom
<nahom> How are you today?
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<NiteHawk> i'm fine thanks
<nahom> Yet again, I'm here to trouble you...
<NiteHawk> :D feel free to do so
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<nahom> The M3 has A20 dual core processor and Mali GPU and also WiFi
<nahom> I did lshw and it's showing me that the second core is DISABLED
<nahom> I also want the WiFi to work....
<nahom> Can you give me an overview of how to go about finding and installing drivers for the hardware?
<NiteHawk> ok, the 'missing' cpu core might be related to u-boot (psci) support. can you pastebin the output of " dmesg | grep -E 'psci|started in' "?
<nahom> Umm... what's the simplest way to get output from the M3 on to my main PC?
<NiteHawk> if you have it networked: a ssh client
<nahom> Yes. I forgot about SSH
<nahom> It is connected to the internet but it has no gui
<NiteHawk> ssh is a text-based protocol ("terminal"), there's no gui involved. to easily access the M3 from your PC you'll either need a network connection (ssh) or a serial cable (http://linux-sunxi.org/UART)
<NiteHawk> normally ssh will do nicely (once it's setup properly), as there's no extra hardware involved
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<nahom> NiteHawk: I was setting up openssh and stuff and creating a new user and adding to sudoers list. I'm all done now. Here comes the output of the command
<oliv3r> wens: do you know by head, if our mmc hardware/driver supports DDR mode?
<nahom> login as: nahom nahom@192.168.1.200's password: Welcome to Ubuntu 14.04.3 LTS (GNU/Linux 4.2.0-rc7 armv7l) * Documentation: https://help.ubuntu.com/ Last login: Thu Aug 27 11:19:44 2015 from 192.168.1.10 nahom@m3:~$ dmesg | grep -E 'psci|started in' [ 0.000000] psci: probing for conduit method from DT. [ 0.000000] psci: Using PSCI v0.1 Function IDs from DT [ 0.003860] CPU: All CPU(s) started in HYP mode. nahom@m3:~$ [
<NiteHawk> nahom: that looks okay, i wanted to make sure you have psci present (it is), and that HYP mode is used
<nahom> What's next?
<nahom> *-cpu:0 description: CPU product: cpu physical id: 0 bus info: cpu@0 size: 960MHz capacity: 960MHz capabilities: cpufreq *-cpu:1 DISABLED description: CPU product: cpu physical id: 1 bus info: cpu@1 size: 960MHz capacity: 960MHz capabilities: cpufreq
<nahom> that's the output from lshw
<NiteHawk> what does "cat /sys/devices/system/cpu/online" say?
<nahom> NiteHawk: 0-1
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<NiteHawk> that means "CPUs 0 to 1 online", so there's your two cores. maybe lshw is getting it wrong somehow... i'll try to do a quick cross-check on my A20
<nahom> Ok...
<nahom> How do I get the radio working?
<NiteHawk> you can also look at "cat /proc/cpuinfo", it should list both cores
<nahom> Yes, cpuinfo is showing both... I guess lshw got it wrong
<NiteHawk> according to the wiki, M3 uses a RTL8188 wifi chip. that's pretty much standard and should be nicely supported in the mainline kernel. you may have to adjust your kernel configuration accordingly to include necessary components (make menuconfig)
<nahom> So, I'll have to recompile?
<nahom> First time around, I didn't touch any of the options in menuconfig... I just went with the defaults.
<NiteHawk> you may also need the required firmware files (binaries) for that driver
<NiteHawk> i'd have to check the default configuration for M3, but i doubt it comes with WiFi enabled (i may be wrong though)
<NiteHawk> ok. same here: lshw B.02.17 shows "cpu:1 DISABLED", but it's definitely working
<nahom> So, shall I also change any other configs when I recompile?
<NiteHawk> you need the wireless driver itself, and the standard wireless options - usually that would be stuff like CONFIG_WIRELESS, CONFIG_CFG80211, CONFIG_MAC80211, CONFIG_WLAN
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<nahom> Ok, I'm going to give it a try
<nahom> NiteHawk: One question, so everytime I need to install a driver, I'd need to recompile the kernel? Can't I inject them or add modules?
<nahom> Also, are there any other settings I should change from the default in the menuconfig to make things better?
<NiteHawk> you can compile them as modules, but you'd nevertheless require a kernel configuration that *supports* them in the first place
<NiteHawk> the default sunxi_defconfig is somewhat minimalistic, to support a broad number of devices. if you need support for specific hardware, it's likely that you need to enable it first via make menuconfig
<nahom> Ok, I understand that.
<NiteHawk> wifi is one example, another would be the infrared receiver present on the M3
<nahom> Asides from hardware support, are there other options I should change to increase stability/efficiency/speed etc?
<NiteHawk> with a recent mainline kernel (4.0+) you have cpufreq support for the A20 - that's something i wouldn't want to miss. apart from that it's mostly your personal choice
<nahom> What should I do with the cpufreq?
<NiteHawk> nothing, it's supported 'out-of-the-box'. you can compile the "cpupower" utility (from the kernel sources' tools/power/cpupower subdir) to tweak settings, but that's optional
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<montjoie> hello I seek people who use the Security System driver, for testingif they hit the same bug than me.
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<plaes> montjoie: which bug?
<montjoie> a corruption bug that I try to solve, could you try https://github.com/montjoie/cryptotest
<montjoie> and run cryptodev_test test aes 1000
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<NiteHawk> ssvb: thanks for your reply wrt SPL detection of FEL. as my understanding it that's the SPL proper, does this information get passed to the main U-Boot binary anywhere? or maybe would the fel utility ("uboot" command) be able to mark this case somehow? i'm asking because i'm trying to think of ways to improve FEL boot support within U-Boot, especially the ability do do some selective "source ${scriptaddr}" in case of a FEL boot
<plaes> montjoie: is it missing af_alg library?
<plaes> s/library/directory
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<plaes> configure.ac:50: error: required file 'af_alg/Makefile.in' not found
<ssvb> NiteHawk: the same check can be done in the main u-boot binary- have a look at the old RFC patch - https://patchwork.ozlabs.org/patch/442759/
<ssvb> NiteHawk: we can do it a bit better though, without relying on reserving the address 0x43100000 for boot.scr
<wens> oliv3r: it should, but you first have to figure out how to drop it into 1.8V mode
<wens> that part i really don't know
<NiteHawk> ssbv: interesting stuff - i'll have to go through all of that, thanks. currently there's no other/"direct" way to pass some 'parameter block' from SPL to U-Boot, right?
<NiteHawk> ssvb: btw - that's another area with room for improment. how do we get the "fel" utility to know about / keep track of those magic addresses (to ensure they stay consistent with u-boot)
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<montjoie> plaes: oups I believed to disable the build of af_alg tool, I will update the git
<ssvb> NiteHawk: I can post a reply to the mailing list with some ideas about this
<montjoie> plaes: updated
<plaes> yup.. will test
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<plaes> ugh..
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<oliv3r> wens: DDR mode doesn't work on 3.3V mode?
<plaes> montjoie: something like this: Decrypt error at request 0 pos=270448 of len=524288 key=16
<oliv3r> wens: then the 1.8V problem is interesting, a) the olimex for one doesn't even have 1.8V i think; b) does the mmc infratructure offer a way of dropping to 1.8V mode (via a gpio for example?)
<plaes> I actually did with 'aes test 2' because 1000 was taking too much time :P
<plaes> now running 1000 again
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<montjoie> plaes: ok thanks, it is confirming the bug
<plaes> btw, did you see other day that I had troubles with enabling openssl stuff via af_alg?
<plaes> looked like hash algorithms were getting enabled
<plaes> but not crypto
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<montjoie> I see but I never tested the AF_ALG engine for openssl
<plaes> ok
<montjoie> perhaps you need to set the list of cipher for the engine in openssl.cnf
<plaes> I had, but it might had been wrong :S
<plaes> will recheck if the current aes test finishes
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<wens> oliv3r: afaik, ddr is 1.8v
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<plaes> how much time should the 'aes 1000' take?
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<oliv3r> ah maybe yeah, but we dont have gpio or pin support in software or in the mmc hardware, do we?
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<oliv3r> wens: or rather i could find anything in the mmc bindings docs
<oliv3r> so it may only work if the mmc ip has a pin for it?
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<oliv3r> wens: ddr is 1.5 on the lime2
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<oliv3r> wens: emmc datasheets state 1.8 or 3.3 for vccq, and there is an mmc register Power class 52mhz ddr 3.3v
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<wens> oliv3r: hmm.. didn't know that
<wens> anyway, seems no one ever tried to support
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<plaes> montjoie: and test with 1000: http://fpaste.org/260191/06930881/
<plaes> with 'test aes 1' it alway seems to be key 16
<montjoie> plaes: the test end on first fail,so it do not check aes 192 and aes 256
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<plaes> oh ok
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