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<Cerpin>
Right, I have a working makefile for use with verilator, and have confirmed my CXXFLAGS are getting used -- I've tried passing both -ggdb and -g3 and neither has gotten me line numbers for use with gdb in the final execuatable
<Cerpin>
Is there something else I'm missing here?
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<sorear>
https://github.com/freechipsproject/rocket-chip/pull/1901 looks like an optimization I've wanted for quite some time, I'm curious if it makes a material difference with FPGA flows or if the crap is fully optimized out /cc daveshah
<sorear>
a minimal rocket-chip used to be 50% debug module by line count at the firrtl/verilog levels due to a read-only register getting instantiated 1023 times
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<keesj>
emeb_mac: nice project!
<keesj>
what are you using for video outout?
<keesj>
I am doing the bringup of my up5k based board but currently have problems programming the SPI
<emeb_mac>
keesj: very simple - two resistors sum the sync and luma digital bits into a 3-level composite video signal sufficient to drive a 75ohm video input.
<keesj>
a.. composite .. cool
<emeb_mac>
keesj: what's the problem with spi programming?
<keesj>
(I am atempting SPI master mode) when I hold the chip in reset my SPI clock lines go high and my programmer (buspirate) does can not drive it low
<keesj>
when not in reset I see like 12.5 MHz clocks signal
<emeb_mac>
so you're trying to program the FPGA RAM via spi, as a slave.
<emeb_mac>
rather than loading code into the external spi flash
<keesj>
like the tinyfpga series I will need a bootloader for the normal programming
<emeb_mac>
right
<emeb_mac>
I had some trouble loading my spi flash while the up5k was on the bus too.
<keesj>
emeb_mac: but thinking about it I can indeed perhaps implement FPGA slave
<emeb_mac>
I'm using the FT2232 on a Lattice devboard w/ iceprog to load my spi flash. I let the ft2232 drive the cs/mosi/miso/clk and I pull the CRST high with a jumper
<emeb_mac>
but I also disconnect the FPGA from the flash CS line so it's not contending.
<emeb_mac>
but for most development I've got a custom STM32 board that does USB->SPI for directly loading the FPGA RAM.
<keesj>
do you also experience that the up5k genrally drives lines up while in reset?
<emeb_mac>
keesj: I had some difficulty finding the right combination of levels to set on the FPGA during programming of the spi flash chip, but I wasn't actually looking at what the FPGA was outputting at the time.
<keesj>
emeb_mac: I think I will try you approach(e.g. load directly into ram)
<emeb_mac>
just poking pins until it worked. :P
<emeb_mac>
direct loading w/ the FPGA in slave mode is very easy and pretty fast too.
<emeb_mac>
plus saves erase/write cycles on your flash.
<emeb_mac>
look at the iceprog code for details of how that works
<keesj>
I have been following the http://8bitworkshop.com/ Hardware Design book / webide and part of it was creating a small cpu. pertty cool stuff (and the ide is also great)
<keesj>
following Designing Video Game Hardware in Verilog (not the hardware desin i think that one might be new)
<emeb_mac>
looks fun
<emeb_mac>
it's fairly easy to get 65xx stuff up and running on the icestick - I've done it too.
<keesj>
it is (and the editor is really nice and allows you to follow along) because they have the CRT emulator in the browser
<emeb_mac>
cool
<emeb_mac>
their book seems to have a lot of interesting video stuff in it.
<keesj>
it is best appreciated by first reading the book (going into old 'school game development)
<keesj>
but also the ide is nice because you don't need to write a test bench to see the waveform (you don't need to save to see the impact of your changes) this allow for more fun. the editor also works locally and I have been playing with the idea to combine this with yosys
<keesj>
but first I want to have my board working :P
<emeb_mac>
working hardware is a good thing.
<keesj>
but by now I have a zillion different FPGA boards that all lack some feature
<emeb_mac>
heh - welcome to the club. :)
<keesj>
thanks... I guess
<tnt>
emeb_mac: Nice :)
<emeb_mac>
tnt: it's not exacty "high res" but it works.
<emeb_mac>
and the fun part was getting it working with an SPRAM and no contention between CPU and video.
<emeb_mac>
still 2 SPRAMs left unused. Need to think of something to do with them - maybe an I2S audio wavetable synth :)
<tnt>
emeb_mac: hehe, yeah, I was thinking of that two although with just one SPRAM because I'm using 2 for videos.
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<emeb_mac>
tnt: sounds like your video is a lot more advanced than mine.
<tnt>
well, it's text mode only, but full hd 1080p, takes up memory :p
<tnt>
idea was to be able to do simple graphics in tile based mode. Because for 1080, even the whole 4 SPRAMs wouldn't be enough memeoyr for a bitmap mode.
<emeb_mac>
interesting
<emeb_mac>
so you've got tiles w/ attribs that you can plop down anywhere.
<emeb_mac>
and they're programmable.
<tnt>
yeah.
<emeb_mac>
this is driving one of those HDMI serializer PMODs?
<tnt>
(this was with a single pmod one where I had only 3 bit color :p)
<emeb_mac>
cool
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<emeb_mac>
using lots of dithered tiles I assume?
<tnt>
yeah :)
<tnt>
and the algo to convert the picture to the tiles was probably far from optimal, that was just a quick hack.
<emeb_mac>
good enough for a quick test
<emeb_mac>
zzzzz time - gn
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<keesj>
btw .. I might have spoken with some of you IRL . I was at the https://f-si.org/ conference about two weeks ago
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<guan>
my google-fu is failing me: is there an example somewhere of how to use openocd to program the lattice ecp5 versa board with a .svf or .bit file from migen/nextpnr/trellis? (either using command line or migen.build.openocd.OpenOCD in python)