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_whitenotifier>
[Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) -
https://git.io/fhxmz
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<
_whitenotifier>
[Boneless-CPU] zignig synchronize pull request #3: Text Assembler for boneless (WIP) -
https://git.io/fhxmz
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tnt>
is there some 'cute trick' to implement a signed divide by a power of two with round toward zero in an fpga ?
<
tnt>
So far, adding ((1 << n) - 1) before the truncation by n bits seems to be the best I can come up with.
<
sorear>
I'm pretty sure you can't do this without an adder
<
Ultrasauce>
isnt a signed shift sufficient
<
tnt>
Ultrasauce: -1 >> 2 = -1
<
tnt>
in DSP stuff that introduces a slight negative bias
<
Ultrasauce>
oh duh
<
Ultrasauce>
use one's complement? :)
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sorear>
As if a bias towards zero is better?
<
tnt>
in SDR a negative bias shows up as a DC component in your signal :/
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TD-Linux>
if you look at libopus, rav1e, etc you will also see it
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gruetzkopf>
hmm, someone have a kicad symbol/package for LFE5UM5G-45 in caBGA381 around?
<
q3k>
you can generate them
<
q3k>
with some unholy python scripting
<
gruetzkopf>
yeah i've seen that script (for the package)
<
q3k>
use my fork because the upstream lattice code is broken
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whitequark>
gruetzkopf: ECONNREFUSED from here
<
whitequark>
where is it hosted?
<
gruetzkopf>
DO FRA1
<
gruetzkopf>
v6 or v4 broken?
<
TD-Linux>
gruetzkopf, protip, turn on opengl and 2x msaa
<
gruetzkopf>
yeah, fresh install on this laptop
<
TD-Linux>
kicad nightly is broken with hidpi :( might have to submit a patch
<
gruetzkopf>
this thing is gonna need some editing to be KLC compliant