<mrec>
does anyone know is there any problem when using fifodc and the ECP5? I have set up 16kx24b and the output is totally wrong (input 42mhz, output = max 180kbyte when dividing 42mhz/24)
<mrec>
well the output as long as it gets through seems to be correct but the bandwidth is wrong
<mrec>
I have never seen something like that with the xo2/xo3
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<mrec>
bying this ecp5 evb from lattice was just wrong... even the raspberry pi connector is wired up the wrong way, and clocks are not connected where they should
<mrec>
the machxo evns can be directly connected to the raspberry pi without any adapter on that ecp board you need to add 2 pinheaders in between because the connector is the wrong way around
<mrec>
and they did not use a clock input for the raspberry pi spi clock
<mrec>
that whole pinout just does not make any sense
<mrec>
but why the fifo is not getting filled .. I'm using lattice diamond (i know that might not be the right channel for it).. so weird
<Flea86>
mrec: You could simply oversample that spi clock using a fast internal clock, no? I realize it isn't ideal...
<mrec>
Flea86: I'm using another pin for that and the spi part is ok but the fifo is still a problem
<whitequark>
19:36 < TD-Linux> had to laugh that even fosdem attracted a few suspcious-of-open-tools people
<whitequark>
how does that work
<Flea86>
but I agree that isn't good - I seem to recall some Lattice FAQ note explaining how to feed a non-global clock into the FPGA.. something about setting said input to a generous timing jitter value (didn't work for me..)
<mrec>
spi is running at 66mhz here. the other data input is running at 45mhz
<mrec>
I'm trying to transfer the data from the slow to the fast clock (without success)
<Flea86>
mrec: Are you using opentools or Diamond tools?
<mrec>
the spi protocol dumps 180kbyte valid and 7mb empty data
<mrec>
Flea86: diamond (I know this channel would be for the opensource one, just wonder if someone has seen some issues with lattice's dcfifo before)
<Flea86>
I've not had any issues with fifodc myself.. but I've not pushed them too hard beyond a few innate video apps
<mrec>
I think even though the fifo is set to 24 bit it's more like transferring like 8bit and or dropping a lot
<Flea86>
mrec: Also, I only use Synplify Pro, not the Lattice Synthesis Engine
<Flea86>
if that helps
<whitequark>
what's fifodc?
<mrec>
diamond is set to synplify
<Flea86>
Dual clock FIFO block iirc
<mrec>
dual clock fifo?
<Flea86>
mrec: What version Diamond are you running?
<mrec>
the latest one.
<mrec>
with the 1 year eval license which comes with that board
<Flea86>
Ok. I'm still using 3.10 here
<Flea86>
Have you tried simulating your code?
<Flea86>
Timing report?
<mrec>
the simulation seems to be ok
<mrec>
the same data feeder description has no problem with the xo2/3
<mrec>
think I'll just dump that evn today and go back to the xo2/3
<Flea86>
Ah, so you've tried practically the same code on the xo2/3 and that works? Interesting.
<Flea86>
Are you sure you have your fifodc configured properly?
<mrec>
yes
<Flea86>
Most of my problems with FIFOs have been issues with their configuration
<mrec>
I have no idea anymore... 3days debugging and trying to break things down and still no success
<Flea86>
using clarity designer etc.
<Flea86>
Bummer :(
<Flea86>
mrec: Does it synthesize properly using LSE?
<mrec>
write address depth 16384 data width 24
<mrec>
on the xo2 I have used a much lower depth
<Flea86>
Does scaling the FIFO back change matters?
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<_whitenotifier-c>
[Glasgow] whitequark unassigned issue #98: Export production files for revC0 - https://git.io/fhH6s
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<mrec>
think my protocol is just crap, I need to rework that... fitting a dynamic bandwidth into a static bandwidth
<_whitenotifier-c>
[whitequark/Glasgow] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/fhHN5
<_whitenotifier-c>
[whitequark/Glasgow] whitequark 13815e5 - cli: for build, --rev is required.
<TD-Linux>
whitequark, I think some people are there more for risc-v. there was one comment of "how can migen possibly surpass verilog when verilog has 40 years of development into it???"
<TD-Linux>
I'm actually pretty used to similar comments in my field (free software impls of free vs patented codecs) so it's funny to see then appear other places :)
<q3k>
i only hear this argument regularly about ida pro
<sorear>
i'm not quite following how risc-v is relevant to the question. are you saying that "fosdem people" are obviously pro-fos but having the risc-v track attracted "non-fosdem people" ?
<TD-Linux>
I can't split it like that because everyone there was a "fosdem person"
<TD-Linux>
but yeah different people there are interested in freedom at different layers of the stack
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<q3k>
my theory is that a lot of those people have gone through their life telling themselves that it's okay to use proprietary ip cores / architectures / toolchains because obviously it's impossible to have that open source
<q3k>
and now that they're proven wrong they're clinging on to the silliest arguments just because it's easier to continue the lie than to change your point of view
<q3k>
even worse, their careers might depend on these staying proprietary
<q3k>
so they might feel like you're violating their sacred space of 'no way you can do this, it's too difficult' by just comint in with f/loss software like that
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<whitequark>
i love it
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