<fraktor>
Question about Zig's async model; do I need to explicitly insert suspension points, or will that happen automatically?
<pixelherodev>
Explicit only, IIUC
<daurnimator>
fraktor: depends. only the lowest level code needs to insert them. all callers get them inserted automatically
<daurnimator>
s/lowest/innermost/
<fraktor>
daurnimator: I see. I've been reading up on Python's async model and it seems similar.
<fraktor>
So if I do some intense computation that doesn't do any I/O or anything else that can be async, I need to insert suspension points myself, right?
<daurnimator>
fraktor: IIRC python's async model requires explicit `async`/`await` annotations
<fraktor>
But I do need to add suspension points myself if I'm not using a low-level function that does, right?
<daurnimator>
yes. in that case you *are* the low-level function
<daurnimator>
but those are usually part of the event loop implementation or OS-level wrappers
<daurnimator>
we should almost never see them in user-level code
<fraktor>
Even if I'm doing intense and slow number crunching and want other "threads" to be able to do their thing?
<daurnimator>
fraktor: then you would call a function from the event loop implementation that somewhere deep inside has the actual `suspend` keyword.
<fraktor>
I see. Does Zig come with an event loop? (I'm super new to all this_)
<daurnimator>
Yes; though it's not well documented, bug free, or fast. i.e. its a usable work in progress
<daurnimator>
(just like the rest of the language)
<fraktor>
Makes sense. I really can't wait until the language is more mature, since it's really nice to use already, but a bit too volatile for big projects.
<daurnimator>
fraktor: the best way is to contribute in an area you have experience/expertise
<fraktor>
I have in the past, a couple times.
<fraktor>
I've gotten a busy schedule recently, but I'm probably going to have more time in the future to contribute.
<FireFox317>
i'm also trying to run zig on fpga's :P
<leeward>
Like on an ARM core on an FPGA? Or are you trying to field-program some gate arrays with it?
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<scientes>
FireFox317, well this is risc-v
<scientes>
also compiles to 560 bytes
<FireFox317>
leeward, I have an Xilinx Zynq board which has a dual-core armv7 cpu and programmable logic on the die. Running Zig on the arm core's is pretty easy, but now i'm working on running zig on a riscv-softcore inside the programmable logic and talking to the arm core over an AXI interface.
<ikskuh>
:O
<scientes>
FireFox317, directly to the risc-v or through memory?
<scientes>
as that looks like it is tied to wishbone
<scientes>
>
<scientes>
support for atomic operations.
<scientes>
oh wow, cool
<scientes>
this is pretty complete stuff
<FireFox317>
ikskuh, my todo list also consists of putting a spu-core in the programmable logic and programming that one with zig (stage2) :P
<ikskuh>
haha neat!
<ikskuh>
i have a semi-compliant core in VHDL
<scientes>
what language does it run?
<FireFox317>
scientes, his own isa (spu-2 iirc?)
<ikskuh>
yeah, right now i only have a assembler
<ikskuh>
FireFox317: if you start doing this, ping me in #spu-mark-ii ;)
<FireFox317>
scientes, through memory i guess. Let the soft-core do a specific task and use the arm core for visualisation and stuff
<danyspin97>
how can I initialize a [:0] ?
<scientes>
FireFox317, I was wondering how I could write a little asic and have it do its own DMA
<scientes>
and how to call it from a soft-core
<scientes>
people are using llvm to write GPU+CPU stuff
<scientes>
so this stuff should be really standard by now
<ikskuh>
scientes: what do you mean by ASIC here?
<scientes>
ikskuh, just verilog
<ifreund>
danyspin97: a null-terminated array literal
<ikskuh>
ASIC is just another Tech similar to FPGA, both can implement pretty much the same
<ikskuh>
danyspin97: slice something with terminator:
<ifreund>
[_:0]u8{1,2,3};
<scientes>
ikskuh, yeah, ASIC means actual silicon, but I am trying to talk about how things communicate
<ikskuh>
var some = "hell\0 world!";
<ikskuh>
some[0..4 :0]
<ikskuh>
scientes: that's why i was wondering…
<scientes>
ikskuh, like the FOMU is unusual as the FPGA is hooked up directly to the USB pins
<danyspin97>
ifreund, ikskuh: what about heap vars?
<scientes>
which means you can implement a HID or mass storage device
<FireFox317>
ikskuh, sure will do (i'm still in the phase where i'm figuring out how everything works) this zynq chip is quite complex :D
<scientes>
FireFox317, have you checked out if the open source symbiflow toolchain works?
<scientes>
oh nvm, they don't have any zync support yet
<ikskuh>
danyspin97: same difference, you can create a zero-terminated slice out of any normal sliceable type that contains a zero. if there isn't a zero, it will crash
<scientes>
but they do have 7-series support
<scientes>
so if it is 7-series you could help them out :)
<ifreund>
danyspin97: allocate however much memory you want then write whatever you want to it
<FireFox317>
yes i'm in the #symbiflow channel and saw you were in some other channels to (##openfpga, #yosys)
<ikskuh>
note that arrry with terminator do have a zero terminated slice already
<FireFox317>
scientes, ^^
<danyspin97>
ifreund, ikskuh: I see... not trivial though. Using a stack var is simpler in this case
<FireFox317>
scientes, yeah there is support for zynq fpga's in the symbiflow toolchain. I managed to get blinkly led working on the zynq
<FireFox317>
however, there is not a good example yet
<scientes>
FireFox317, can you blink it from the arm core?
<FireFox317>
yes :D
<scientes>
oh sweet
<ikskuh>
danyspin97: it doesn't matter if you use a stack or a heap var. same difference
<FireFox317>
scientes, i'm working on an example which i will add to symbiflow-examples i think
<FireFox317>
scientes, you have an fomu?
<scientes>
yes, and I just bought a litefury
<scientes>
when i found out it shuts down on overheat as I can't fit the heatsink in my laptop
<FireFox317>
scientes, ah i see, artix7. so you basically want to have a soft-core running in the fpga logic as a co-processor for your main laptop cpu?
<scientes>
maybe I could also just use a serial port type thing
<FireFox317>
serial port over pcie?
<scientes>
my problem with the fomu is that it is too difficult to build
<scientes>
especially when you have to put a usb stack on there to communicate at all
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<FireFox317>
scientes, yeah a simple uart interface is way easier ofcourse. But regarding the fomu it's really nice that you can use a complete open-source toolchain for the ice40. This is not yet the case for the xilinx 7-series chips (artix, zynq etc)
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<FireFox317>
scientes, well its possible as i said before, however a lot of the bitstream documentation is not yet reversed engineered (for the xilinx chips)
<scientes>
only stuff that doesn't exist on ice40 however :)
<scientes>
FireFox317, the problem is that reading these standards has nothing to do with my project
<FireFox317>
true that :P and P&R is way harder because the chip is way bigger (VPR is used for xilinx chips instead of nextpnr) however daveshaw started working on a nextpnr-xilinx
<FireFox317>
scientes, reading usb and pci-e standards?
<scientes>
i want it to feel a little more like programming linux, when I can just program to an interface, rather than have to bootstrap myself
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<FireFox317>
scientes, i see. I think this has to do with the background of most fpga users. They are more hardware oriented (like me, electrical engineering) and thus the high-level interfaces that software people are used to do not really exist at the fpga level yet. However with the increasing popularity of open-source fpga toolchains this is definitely gonna change i think.
<leeward>
I think the constraints there are more around the resources available on the fpga than the toolchain. If you have enough gates, you can give your soft core a bunch of SRAM and run an operating system. Or put a memory controller on it and talk to external DRAM. It's more about what you get and why you're using an fpga in the first place.
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<scientes>
FireFox317, it would be nice if the open source tools supported the serializer/deserializer
<scientes>
and that would be a natural interface
<scientes>
leeward, except the whole reason I am interested in FPGAs is that you DONT have to implement a stack machine
<scientes>
sequential stack machine
<FireFox317>
scientes, you mean the serdes interface on the 7-series? (ISERDES and OSERDES)?
<scientes>
yeah
<scientes>
the next generation of CPUs are also moving to serial ram interface
<scientes>
because ram is now taking up like half of the pins on a CPU, and is limiting bandwidth
<scientes>
so those pins are going to be offloaded onto a ram controller