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<tnt>
Is 100% compatibility with official lattice primites something that's required ? Would a 'INIT_FILE' param on the ice40 EBR primitives be accepted for merge ? (rather than all the INIT_xx params) ?
<daveshah>
I'd be fine with that
<daveshah>
We aren't 100% compatible atm because we don't have the RAM meta-primitives
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<kc5tja>
ZipCPU: yt? I seem to remember you had a webpage on the topic of Yosys and initializers for the iCE40-family of FPGAs. Am I misremembering?
<ZipCPU>
kc5tja: Not sure I'm remembering what you are referencing. What are you looking for?
<kc5tja>
I seem to recall an issue between iCE40 family of FPGAs and Yosys where initial statement values were required to be 0.
<ZipCPU>
That's been fixed
<kc5tja>
It had something to do with the way the flipflop architecture was implemented on the die.
<ZipCPU>
The issue was that all registers on the H/W must be initialized to zero. Yosys now quietly inserts inverters and adjusts the logic to make things work
<kc5tja>
Ooh, got it. Thanks.
<ZipCPU>
Not sure I ever discussed it on the ZipCPU blog tho
<kc5tja>
Not sure where I remembered seeing it. I was just wondering because I'm contributing some documentation for nmigen and wanted to cover that special case. But if it's not special anymore, I can remove that footnote.
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<ZipCPU>
Nope, not a special case--remove the footnote
<ZipCPU>
The big issue I discussed on the blog was the lack of distributed RAM in the iCE40's
<ZipCPU>
You can't read from the RAM therefore without using a clock.
<ZipCPU>
always @(posedge i_clk) if (condition) value <= mem[addr]; works, but always @(*) value = mem[addr]; will not
<kc5tja>
nods
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<cr1901_modern>
Sure "always @(*) value = mem[addr];" will work. You'll just lose half your LUTs just to implement 32 bytes of RAM :D
<kc5tja>
*Something* has to keep those LUTs busy. My house won't stay warm on its own. :)
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<tnt>
you can use the falling edge to kind of fake it ... but you'd better not expect to run very fast :p