clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
lutsabound has quit [Quit: Connection closed for inactivity]
_whitelogger has joined #yosys
_whitelogger has joined #yosys
<ZipCPU> cr1901_modern: You work with migen, right?
<ZipCPU> I'd like to reference it on a blog page. What link do you think would be the best landing page for FPGA designers who've never heard of it before?
<cr1901_modern> ZipCPU: http://m-labs.hk/migen/index.html
<ZipCPU> Thanks!
<cr1901_modern> Also https://www.wdj-consulting.com/blog/migen-port.html "What Is Migen- And Why Use It?" section (disclaimer: this is my own website)
<ZipCPU> I'm drafting an article, and it includes a user referencing Migen.
<ZipCPU> He asks if Migen will one day get a formal verification capability added into it.
<ZipCPU> Do you see this happening at all in the future?
<cr1901_modern> Everybody's asking about this all of a sudden
<cr1901_modern> https://twitter.com/trc_wm/status/1038521062751916033 are you talking about this? or is this a completely separate user?
<cr1901_modern> No less than 5 ppl have asked about formal in migen in the past week
pie_ has quit [Remote host closed the connection]
<awygle> wow migen is more popular than I thought. actually both migen and formal are lol
pie_ has joined #yosys
pie_ has quit [Ping timeout: 240 seconds]
pie_ has joined #yosys
seldridge has joined #yosys
_whitelogger has joined #yosys
azonenberg_work has quit [Ping timeout: 244 seconds]
azonenberg_work has joined #yosys
rohitksingh has joined #yosys
_whitelogger has joined #yosys
X-Scale has quit [Ping timeout: 252 seconds]
emeb_mac has quit [Ping timeout: 272 seconds]
X-Scale has joined #yosys
seldridge has quit [Ping timeout: 240 seconds]
dys has quit [Ping timeout: 272 seconds]
maikmerten has joined #yosys
rohitksingh has quit [Quit: Leaving.]
ravenexp has quit [Quit: WeeChat 2.2]
_whitelogger has joined #yosys
dys has joined #yosys
_whitelogger has joined #yosys
ym_ has joined #yosys
_whitelogger has joined #yosys
dxld has quit [Quit: Bye]
dxld has joined #yosys
lutsabound has joined #yosys
fsasm has joined #yosys
rohitksingh has joined #yosys
maikmerten has quit [Remote host closed the connection]
rohitksingh has quit [Ping timeout: 252 seconds]
X-Scale has quit [Quit: HydraIRC -> http://www.hydrairc.com <- Now with extra fish!]
rohitksingh has joined #yosys
GuzTech has joined #yosys
rohitksingh has quit [Quit: Leaving.]
emeb_mac has joined #yosys
<shapr> it's that time again
<awygle> aaaadVENTURE TIME!
rohitksingh has joined #yosys
<shapr> awygle: heh, I was thinking it's time to spend ten hours doing FPGA stuff, but yeah!
<qu1j0t3> shapr: Yeah!
<shapr> most FPGAs include at least one phase locked loop, and that's where you get the clock signal, is that correct?
_whitelogger has joined #yosys
<qu1j0t3> sounds about right.
* shapr thinks about that
<shapr> Is there a tool where I can give it the boolean truth table and get back the logic expression?
<sorear> you’d more likely write that as a case statement or array access
<sorear> that’s standard functionality of synthesis tools
<shapr> sorear: got an example?
<sorear> not handy
<awygle> shapr - you can get clocks from other places too (like discrete crystals) but the PLL can clean up jitter or produce rational clock multiples and whatnot
<awygle> as for 7-seg I'd just declare an array of 16 7-bit vectors and index. Something like....
<awygle> reg [15:0] lookup [6:0];
rohitksingh has quit [Quit: Leaving.]
<awygle> Then use an initial for loop to initialize it
<awygle> Hopefully that gets compiled down into LUT equations during synthesis
rohitksingh has joined #yosys
<awygle> Err 3:0 not 15:0, derp
<shapr> awygle: for loop to initialize? huh?
<shapr> oh I'm starting to understand
rohitksingh has quit [Quit: Leaving.]
AlexDaniel has quit [Ping timeout: 244 seconds]
<awygle> hm I just realized this but how do you tell the difference between B and 8
azonenberg_work has quit [Ping timeout: 252 seconds]
<adamgreig> 'b'
<adamgreig> (and 'd' and '0')
<shapr> right, I was going to use 1-9 and A b C d E F
<shapr> I was thinking about that on the treadmill this morning, how to make 1-F with only seven segments
<shapr> I wish these pmod boards had the many many segments
<adamgreig> the starburst displays
<shapr> right, whatever those are called
<adamgreig> for perfect hex :p
<shapr> yeah!
<shapr> I could also make really loading animations and that kind of thing with the starbursts
maikmerten has joined #yosys
<awygle> Oh that's irritating
<awygle> Lol
<awygle> But yeah necessary
<awygle> It's extra irritating because you could do all lower case except A
<awygle> (admittedly lowercase and uppercase F look the same on a 7seg)
<adamgreig> not sure about lowercase e either :P
<awygle> It'd be a bit deformed lol
<awygle> Backwards 9
<adamgreig> uppercase E with one extra segment
jn__ has joined #yosys
<shapr> yeah, I wish I could get pmod boards for that
<adamgreig> just get one of the hdmi pmods and use a 1080p lcd panel :P
<shapr> We have some vga pmods
<shapr> I started on my own set of tutorials, but there's so much I don't know
azonenberg_work has joined #yosys
<shapr> I think I'll skip out and use the hackaday fpga tutorials
<shapr> I know my coworkers will want something about audio processing
<shapr> and I have a mems microphone and an i2s stereo in/out board
<shapr> I want to start out with a motivational example that will encourage them to stick with these classes
<awygle> Synthesizers are common projects and are very cool
<shapr> oh that's a great idea!
* shapr searches for i2s verilog synthesizers
<shapr> mithro: oh hey, you're the mithro mentioned in the NeTV2 updates?
<mithro> shapr: Yes
<shapr> wow, cool!
* shapr starts reading https://hdmi2usb.tv/home/
<shapr> oh man, I need this
pie__ has joined #yosys
<shapr> mithro: how can I throw money at TimVideos?
<mithro> shapr: In what way?
<shapr> I give weekly lightning talks, and we're using OBS and it's meh, but TimVideos looks much cooler
<shapr> is there a patreon or other way to send some money your way?
<mithro> shapr: The big thing we need is more developers :-P
<shapr> hm, I do have an NeTV2 ordered, and I'm slowly learning FPGA dev
<shapr> ok then, I'll add it to my long list of things to do
<mithro> shapr: A lot of our development is less FPGA development and more things like infrastructure, documentation, etc
<shapr> ah, that I can do
pie_ has quit [Ping timeout: 252 seconds]
<mithro> shapr: Ha, I totally forgotten about that :-P
<shapr> it's perhaps the best onboarding guide I've seen for a foss project
<mithro> shapr: I'm still not happy with it
<shapr> how could it be better?
<mithro> shapr: A lot of the "Find more information about;" sections are empty
<shapr> fair enough
<mithro> shapr: It's a bit out of date
<mithro> shapr: Also want to rework the litex-buildenv stuff
* shapr reads up on LiteX
<shapr> ok, now I have to yank my focus back to reading through the Hackaday FPGA lessons, since I'm teaching them tomorrow
<mithro> shapr: were are you based?
<shapr> mithro: atlanta! Where are you?
<mithro> Bay Area at the moment
<shapr> I'm a professional programmer working in a company with about a hundred devs
<shapr> I've never done FPGA anything, but I love teaching classes.
<shapr> Right now I teach Tuesday Haskell, and previously I've done Monday Python, for any employee
<shapr> I'm easily distracted, but when it comes to giving a presentation or teaching stuff to others, suddenly I have more focus.
<shapr> mithro: you going to ICFP/strangeloop?
<mithro> nope
<mithro> I'm not a haskell / functional person
<shapr> strangeloop isn't fp-specific that I know of
* shapr checks
<shapr> "Strange Loop is a multi-disciplinary conference that brings together the developers and thinkers building tomorrow's technology in fields such as emerging languages, alternative databases, concurrency, distributed systems, security, and the web."
<mithro> only people I know who go to it are fp people
<shapr> oh, who do you know in the fp world?
<shapr> I haven't been to ICFP in 12 years, looking forward to meeting a bunch of internet people I've not met in person
<mithro> shapr: I'm very skeptical of haskell and similar languages - much more happy with things like Python
<shapr> fair enough
<shapr> Python was my 'first love' in programming languages, I get it.
<awygle> i... don't like python
<awygle> even though i write it a lot
<mithro> awygle: I would say that about C/C++ :-)
<awygle> mithro: there are undeniably bad things about C and C++, but they're much more shaped like my brain than Python is
<awygle> in particular, the module system of python is _bananas_
<awygle> i have never gotten anything nontrivial to work first time, ever
* shapr shrugs
<shapr> It really is what you're used to, in my experience.
<shapr> I'm not convinced any programming languages are "natural"
<awygle> yeah that's why i use the term "shaped like my brain". i'm aware it's very me-centric
maikmerten has quit [Remote host closed the connection]
dys has quit [Ping timeout: 272 seconds]
digshadow has joined #yosys
<qu1j0t3> shapr: however, some are unnecessarily painful.
<mithro> qu1j0t3: *cough* verilog *cough* :-P
<awygle> verilog is really not that bad. `default_nettype notwithstanding
fsasm has quit [Ping timeout: 245 seconds]
_whitelogger has joined #yosys
GuzTech has quit [Ping timeout: 245 seconds]
danieljabailey has quit [Quit: ZNC 1.6.5+deb2build2 - http://znc.in]
danieljabailey has joined #yosys
seldridge has joined #yosys
seldridge has quit [Ping timeout: 252 seconds]
lutsabound has quit [Quit: Connection closed for inactivity]
lutsabound has joined #yosys