clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> for multiclock induction that FAILED , why would the counterexample trace follow exactly the failed assert() which means the assert() seems to be correct ?
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<shapr> ZipCPU: does the yosys suite have a simulator?
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<daveshah> shapr: yes, yosys has a `sim` command built in (see `help sim`)
<shapr> ok, thanks
<daveshah> it's fairly basic, but it's quite useful for quick tests as it can create a stimulus
<daveshah> Yosys doesn't support testbenches per se, nor is it very fast
<shapr> from my coder perspective, is a simulator sort of like inputs to unit tests?
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<shapr> I'm still not sure how all the pieces fit together, but this is helping: https://zipcpu.com/blog/2017/08/21/rules-for-newbies.html
<shapr> Since I'm using a BeagleWire, would I need a hardware logic sniffer? or would I be able to dump data to gtkwave?
<shapr> I bet I need a BeagleWire forum for that question
<daveshah> A hardware logic sniffer and a simulator are very different things
<daveshah> A simulator runs on your computer only, involves no hardware and often no place-and-route or even synthesis
<shapr> ok
<shapr> that clears up several questions
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<dys> I'm trying to setup LVDS input according to lattice TN1253, but getting this error: src/place.cc:1078: void Placer::place_initial(): Assertion `valid(chipdb->cell_location[c].tile())' failed
<dys> any ideas how to debug this further?
<dys> there are no warnings that could hint at what's going wrong
<dys> ah, looks like there's a matching github issue… https://github.com/cseed/arachne-pnr/issues/50
<dys> ja, using PIO3_1B instead of PIO3_1A doesn't trigger the assertion
<dys> yay, my sigma-delta ADC is alive
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<shapr> Anyone know if I can use a PCF file to figure out which pins to turn on/off for a pmod accessory?
<shapr> I have the digilet seven segment display pmod accessory
<shapr> and I have no clue, but I do have some info: https://github.com/pmezydlo/BeagleWire/issues/12
<shapr> that says the pmod pins are reversed, does that mean I need to plug in accessories facing 'down' ?
<shapr> anyone know if pmod headers always have power pins on?
* shapr reads the spec
<shapr> not sure how to use kicad to open the beagle-wire files to see where the pins are all routed :-|
<shapr> oh, I need a more recent version
<shapr> aha, there's a plot in pdf format
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<shapr> IT WORKS!
<shapr> holy crap, I did something with verilog and IT ACTUALLY WORKS
<shapr> that only took ten hours