clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
<mithro> sorear: Using your approach of double signal input, I just realized you can pack both a route on and off the charry chain into one FC cell -- see Figure D on https://docs.google.com/drawings/d/1ZG3eqAp7NrDsf6Ra6zHrVOJyxxCmblpOPVFW8NpE4aQ/edit
<cr1901> Tomorrow's plans: Review temporal induction and how to represent assumptions in SMTv2... because... I forget what yosys does :P.
<cr1901> cc: q3k, thoughtpolice You both should be interested in this
<cr1901> thoughtpolice: A long time ago, I asked "how does temporal induction (where the base case spans over "n" steps/states) relate to mathematical induction (where the base case only considers one step)?" Do you remember a convo like that? If not, I'll check my logs and see if I can find it.
<sorear> if your assumes imply your asserts at time t, and your asserts at time t imply your assumes at time t+1, then your asserts will hold for all time by mathematical induction
<digshadow> trying to do yosys synth_ice40 -vpr but I'm getting a weird error: https://gist.github.com/JohnDMcMaster/507e3b557cbdbcdb36f0884e0be0713c
<digshadow> 1) Does this CLI look correct: yosys -p 'synth_ice40 -vpr -top top -nocarry my.eblif
<digshadow> 2) what is a yosys full design?
<cr1901> sorear: Uhhh, what :)?
<digshadow> fully selected design
<cr1901> digshadow: "fully selected" means "yosys will currently apply transformations on everything in the hierarchy starting from the top level module"
<cr1901> you're able to use the "select" command to force yosys to only apply transformations/passes to only parts of your design
<digshadow> is that not the default?
<cr1901> Yes, but I've never used the -vpr flag
<digshadow> I think the people who have used that flag is around 2 or 3
<cr1901> In any case, firefox takes forever toload on this netbook, so I'll see the gist in about 10 mins or so
<digshadow> uh...are on the 286 or w/e it was
<cr1901> No, I would be signed in as cr1901_286 if I was :). It's an Atom netbook from 2007. I use it when I travel b/c I'm too cheapass to purchase a new "burner".
<cr1901> And I wish firefox ran on 286. Or any browser, really.
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<mithro> digshadow: I have no idea if the order or arguments in Yosys matter
<cr1901> What's weird to me is... I don't know how read_verilog can operate only on fully-selected designs b/c that's how you load a design into yosys in the first place
<mithro> digshadow: If you remove the "-vpr" does the command work?
<digshadow> mithro: I tried moving them around
<cr1901> sorear: More helpfully, I'll need some time to really parse what you said...
<cr1901> As it is, I forget how to represent the concept of an assume in smtv2
<digshadow> ah wait I think there is a typo
<sorear> i don't actually know what "temporal induction" is in any great detail. i think it's close to that
<digshadow> mithro: fixed! works now
<mithro> ?
<mithro> What was the typo?
<digshadow> I accidentally deleted -blif
<mithro> Oh
<cr1901> oops...
<digshadow> I'm not sure what it was doing, but it wasn't what I was trying to do
<mithro> digshadow: Looks like you hit the exact same issue that both myself and cr1901 have hit
<cr1901> what issue was that again?
<digshadow> mithro: issue between keyboard and chair?
* cr1901 coughs
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<mithro> digshadow: So does -vpr give any difference in performance of the vpr output?
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<digshadow> mithro: working on setting up a test to compare multiple vs single abc passes
<digshadow> blinky gave the same for your specific question
<digshadow> but thats not a super involved test
<mithro> Yeap
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<Hail_Spacecake> how does power output from an input/output pin on an ICEStick work?
<Hail_Spacecake> I notice that I can put in a led without a current limiting resistor
<Hail_Spacecake> I don't know if that's bad for the board though
<Hail_Spacecake> the manual says they're 3.3V, but I don't see a max current draw
<awygle> i think they're 8ma
<awygle> 8 mA at 3.3, 6 at 2.5, 4 at 1.8. page 19 of the datasheet
<awygle> Hail_Spacecake: ^
<Hail_Spacecake> is that a different document than the user manual?
<awygle> for the FPGA, not the icestick board, maybe i should have clarified
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<Hail_Spacecake> awygle: ah thanks
<Hail_Spacecake> I'm curious how the syntax for making a pin have a pullup/pulldown resistor works
<Hail_Spacecake> the SB_IO stuff I see in the examples
<daveshah> Hail_Spacecake: pull up is specified as a parameter on an SB_IO
<Hail_Spacecake> what's a SB_IO?
<daveshah> There aren't pull downs in the iCE40
<daveshah> SB_IO is what you put in your Verilog to manually create an IO
<daveshah> With any settings you want
<Hail_Spacecake> I'm looking at https://pastebin.com/7DDk4zQL
<daveshah> I think you can also do -pullup yes in the pcf file
<Hail_Spacecake> it looks like that code is creating a new wire that corresponds to a version of the original input with pullup?
<daveshah> Effectively, you are creating an input buffer with a pullup, rather than letting the tool create the input automatically
<Hail_Spacecake> so there's no way to do a default 0 input
<Hail_Spacecake> but I can always negate the input, right? so that shoudldn't matter?
<daveshah> Yes, or add an external pull down resistor
<daveshah> Either would work, depending on what device you are interfacing with
<Hail_Spacecake> how accurate is the 12MHz clock?
<Hail_Spacecake> can I assume it is exactly 1/12millionths of a second?
<daveshah> I would guess it is better than 50ppm accurate
<daveshah> ie within 0.005%
<Hail_Spacecake> so if I have a LED blink whenever a counter has bit 20 set
<Hail_Spacecake> that divides 12 million hz by 2^20 right?
<Hail_Spacecake> which gets me 11.something hz
<Hail_Spacecake> so, 80 ms
<Hail_Spacecake> er, 87ms
<Hail_Spacecake> but I can clearly see blinking if I do assign output_pin = counter[20];
<daveshah> I think it's actually divide by 2^21 (but I could be wrong)
<Hail_Spacecake> oh 0-counting, yeah
<daveshah> E.g. a 1 bit counter will divide by 2
<Hail_Spacecake> so that's 5.7 Hz
<Hail_Spacecake> or 174 ms
<Hail_Spacecake> I think that's 87ms on, 87 ms off?
<Hail_Spacecake> so yeah that I'd expect ot be able to see
<Hail_Spacecake> or no maybe it's 174 ms on, 174 ms off?
<daveshah> 87ms off, 87ms on
<Hail_Spacecake> so yeah thats visible
<daveshah> Yeah, should be visible but fast
<Hail_Spacecake> counter[19] is blinking really fast
<Hail_Spacecake> counter[18] is like a strobe light
<Hail_Spacecake> that's 22ms on, 22ms off
<Hail_Spacecake> counter[17] is just fliker I can't see unless I get close
<Hail_Spacecake> that's 11ms on/off which I think is below what human perceptoin can do
<Hail_Spacecake> counter[16], nothing visible to me
<Hail_Spacecake> and I should be able to do, like, and(output, counter[16], counter[17]) or something right?
<Hail_Spacecake> looks like it yay
<Hail_Spacecake> thanks for bearing with me while I figure this out, I've basically never touched verilog before
<daveshah> No problem, glad you've got it blinking!
<Hail_Spacecake> I'm gonna try that pll thing you mentioned the other day
<Hail_Spacecake> to get a faster clock
<Hail_Spacecake> woo seems to have worked
<Hail_Spacecake> can you name a module anonymously?
<Hail_Spacecake> I had to do `pll random_name(a,b,c);` to get it to work
<daveshah> Yes, modules have to have a name in Verilog I think
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<mithro> daveshah: Could you take a look over https://docs.google.com/drawings/d/1ZG3eqAp7NrDsf6Ra6zHrVOJyxxCmblpOPVFW8NpE4aQ/edit and make sure that I'm not telling any lies?
<daveshah> mithro: seems correct
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<mithro> daveshah: Do you know if yosys does any LUT optimization? Is that part of what it uses ABC to do?
<mithro> daveshah: Specifically - I'm interested in knowing if it does these -> https://docs.google.com/drawings/d/17nHb4GJcAb4bs98aANaU0GChYlguQdxNBn8KDX2bGsg/edit
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<daveshah> mithro: yes, abc will do loads of stuff before techmapping
<daveshah> Then there will be limited optimisations after mapping in ice40_opt
<mithro> daveshah: Figure 3 is the big one I was wondering about...
<daveshah> mithro: No, there was a PR in arachne in do that
<daveshah> But it could be done in Yosys too
<daveshah> It only happens in limited cases though
<mithro> daveshah: Hrm?
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<cr1901> >abc will do loads of stuff before techmapping
<cr1901> Wouldn't LUT optimization be done _after_ techmapping to SB_LUT4s?
<daveshah> No, ABC will do it using its generic LUT primitives I think
<daveshah> but I don't really know ABC
<daveshah> abc doesn't deal with SB_LUT4s, and Yosys only does some simple opts on them in ice40_opt (like removing LUTs with only const inputs)
<cr1901> Oh, that's what you mean by limited options
<cr1901> limited opts*
<cr1901> I thought you meant "abc does so much that ice40_opt has little left to work with"
<daveshah> I suspect that's also true in most practical cases tbh
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<TD-Linux> which ice40 package is easiest to hand solder? I'd assume the vq100
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