clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<promach> For https://github.com/promach/UART/blob/master/rtl/TxUART.v , what could be the assert() ? it seems to me that this FSM is naturally aligned to next state.
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<Rickta59> on altera it yacks about lines 36->47 having no ';' at the end of line
<Rickta59> and at line 14 it seems confused
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AlexDaniel` is now known as AlexDaniel-
AlexDaniel- is now known as AlexDaniel
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