clifford changed the topic of #yosys to: Yosys Open SYnthesis Suite: http://www.clifford.at/yosys/ -- Channel Logs: https://irclog.whitequark.org/yosys
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<jophish> Hi shapr!
<jophish> the log?
<jophish> How's things?
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<shapr> jophish: how's the verilog? :-)
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<jophish> ah right, not having to write too much of that thankfully
<jophish> clash is doing all the hard work
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<some_other_nick> How are things coming?
<some_other_nick> I noticed that earlier this year support for more ICE40 chips became available, and there are more on the way, barring some I/O issues...
<some_other_nick> Last I checked though, there wasn't much progress on supporting arbitrary chips in place/route, aside from a purely academic project with an arcane XML format for specifying chip architectures.
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