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<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±9] https://git.io/Jv749
<_whitenotifier-3>
[starshipraider] azonenberg 6efa093 - Continued power supply layout
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<azonenberg>
ok, have to do the +7V smps and then i think i'm done with layout proper
<azonenberg>
deleted a few of the ground test points in the original schematic because there were so many of them i didn't think they were needed, they were just taking up space
<azonenberg>
still have to do all of the power pours, but we can get away with pretty non-contiguous plane layout because all of the RF signals are on layer 1 adjacent to a solid ground on layer 2
<azonenberg>
layer 4 is low speed spi command stuff etc, so super nice return paths aren't exactly critical there
<Famine>
i think i have actually increased my intense hatred of web "developers"
<azonenberg>
oh?
<Famine>
we have ~500k people absolutely slamming our provincial governments website, refreshing every 10 seconds... so they came up with an amazing solution, load the first 3mb of crappy java script, then do a javascript redirect to another page with 1mb of favico and pretty pictures ...
<Famine>
to tell you the site is currently down due to heavy traffic. so ~4mb per request
<azonenberg>
...
<Famine>
oh and they are still running analytics but using a client side timer for the redirect, so if the 3rd party analytics are slow you get kicked to a 429
<azonenberg>
...
<azonenberg>
noscript ftw
<lain>
wow that's impressively bad :D
<Famine>
that would work if the entire site wasn't cobbled together in a giant bastard love child between xhr redirects and javascript content frameworks lol
<Famine>
lain, lol yea its amazingly bad, you would think after 5 days of getting hammered they might have said: "lets create an ultra stripped down version of the site to accomplish the 2 tasks that are absolutely slamming our network"
<lain>
they probably literally do not know how to do webdev without some CMS or tons of dependencies that are adding all that bloat
<lain>
"what's html?" :P
<azonenberg>
wait, you mean you can do redirects with a meta tag? you don't need a jquery timer object and a bunch of ajax requests to figure out the url to redirect to? :p
<azonenberg>
here and there in my spare time i've been working on learning modern lightweight web stuff
<azonenberg>
i want to build a website for antikernel labs that is html and css only, no scripting, and is as simple and lightweight as possible while still having a clean, modern look
<azonenberg>
we're talking a few K for the home page
<Famine>
azonenberg, to make it even better, its for emergency benefits if you have been legally forced to self isolate due to covid
<azonenberg>
...
<azonenberg>
Reminds me of some article i saw a while ago saying healthcare.gov contained more lines of code than the entire windows operating system, among other things
<Famine>
so in my province you are legally required to isolate if you have any of the following: cough, runny nose, fever, shortness of breath, sore throat
<_whitenotifier-3>
[starshipraider] azonenberg pushed 1 commit to master [+0/-0/±1] https://git.io/Jv7z3
<_whitenotifier-3>
[starshipraider] azonenberg f08b291 - Finished initial layout. Still have to do power planes and some routing cleanup.
<azonenberg>
might reroute a few things when i fine tune the power fills, but that's the gist of it
<Famine>
haha! 3 hours and i have finally submitted my ID for verification!
<Famine>
now, i have to wait until 9am and spend 3 more hours trying to submit my application for benefits
<Degi>
Huh?
<Degi>
azonenberg: The DAC has 4 outputs, right? are two used by the circuit?
<Degi>
Also whats that footprint with the 5 pins on the upper right which kinda looks like a relay?
<Degi>
Heh cute snail ^^
<Degi>
Maybe you could label the silkscreen a bit more. Like what should be present at test points etc. and the LEDs. (Maybe add a LED to the relay circuit? Idk if its too late for that) On the other hand this is only the characterization board, but later on a nice silkscreen would be neat on the final PCBs heh (and maybe some art on the backside)
<electronic_eel>
Degi: the 5pin thing upper right is the negative power supply module
<Degi>
Neat
<electronic_eel>
azonenberg didn't want to design one with a regulator, but take a full off-the-shelf module
<electronic_eel>
it is quite expensive (~11 $)
<Degi>
Yeh in the next design maybe we can design one
<electronic_eel>
so for the actual scope there will most probably be something else instead
<electronic_eel>
also the fat transistor for the 1v8 discharge rail takes a bit too much space. I've already looked up some alternative parts in sot-89.
<electronic_eel>
I put them on my to-order list and will get them with my next order from mouser. then I can test and compare them to the current one
<Degi>
Is that the one beside GOUT
<electronic_eel>
yes, exactly
<electronic_eel>
Degi: btw, did you do further work on your time-to-digital idea?
<Degi>
Not yet
<Degi>
I only have a spice of that
<Degi>
Should I try to design a PCB?
<Degi>
I found some rather pricy SR latches (5€? dont remember) which would work
<electronic_eel>
would be nice if we could test that together with this afe test board
<Degi>
When I design the PCB, could Azonenberg manufacture it? Because I won't have access to any decent test equipment till this thing is over
<electronic_eel>
I don't know, but I guess it is possible for him
<electronic_eel>
it would probably also make sense to upload the spice files and results, schematics and so on to github or similar so that we can discuss it
<Degi>
Hm I did that in LTSpice which is closed source... What alternatives could you recommend?
<electronic_eel>
I also use ltspice, even if it is closed source. because it works. there is ngspice which is open source, but I had some trouble with it in the past
<Degi>
Hm okay I can uplaod that
<electronic_eel>
I had the issue that often circuits couldn't be simulated in it because they didn't converge. ltspice has some black magic there which inserts some noise here and there to prevent that.
<Degi>
And a bunch of other options which kinda help sometimes, though it can get stuck too
<electronic_eel>
yes, it can also get stuck. then often it helps to use a model from another manufacturer or something to get it to work
<Degi>
So my current design uses a BFP420 as a constant current source to charge a capacitor and two SR latches being driven in quadrature. The latch on the right makes a pulse to set the latches which then get reset by I/Q clock
<electronic_eel>
Degi: I'll look at your design in the evening. my vacation is over and I'm back at work now
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<azonenberg>
Degi: one dac output is unconnected, i was short on space and didnt see a reason to fan out the last one
<azonenberg>
the footprint at top right is a bga smps module for the -7V
<azonenberg>
as far as the tdc goes, i have a 2 GHz 40 Gsps scope so i can measure performance fairly well
<azonenberg>
the LEDs are GPIOs on the MCU, i cant label them more because i havent decided what they'll do yet :p
<azonenberg>
i normally label test points more but i have so many of them, and the board is so dense, i cant fit full text with rail names
<azonenberg>
this board is a one-off i expect to be the only one using, so being super readable isn't a huge deal
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<Degi>
Okay I guess as long as you have the kicad project xD
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<Degi>
Hmm I wonder if...
<Degi>
I think ddc doesnt work in group chats
<Degi>
Hm I designed a SR latch for approx 2 € (for 1 pcs, at 3000 transistors its like 60 cents per latch)
<Degi>
220 ns propagation time but needs like 40 mA
<Degi>
Also for the sampling scope you may wanna keep the comparator within 5 °C
<Degi>
What does 48 dB active gain mean? 10^2.4 voltage gain?
<Degi>
If you wanna have a terasample, within 2 °C (0.45 ps/°C)
<Degi>
Okay I found better cheaper transistors reducing that to 110 ps
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<Degi>
azonenberg: Can your RF simulation program simulate transistors?
<electronic_eel>
Degi: about your time to digital circuit - could you explain the function of the constant current source on the input a bit in more detail?
<electronic_eel>
last time I built a cc source out of single transistors, it required a matched transistor pair on the same die to get reasonable performance
<Degi>
On the input?
<electronic_eel>
otherwise the temp variations and process variations made it ugly
<Degi>
Hm also that schematic is kinda old I completely redesigned it
<electronic_eel>
yes, on the left side
<Degi>
Thats an OR gate on the input
<electronic_eel>
ah, do you have an updated schematics?
<Degi>
V9 makes a 30 ps rise, 20 ps on, 20 ps fall time 350 mV positive pulse and V8 supplies a 25% duty cycle clock
<electronic_eel>
hmm, that will take some time for me to understand ;)
<Degi>
Tow transistors on the top form a SR latch and the two ones below control the SR latch, tiny capacitors and inductors are parasitics
<Degi>
*Two not two
<Degi>
*Two not tow
<electronic_eel>
just a high-level question: you plan to have a comparator on the input, to compare the signal at the output from the regular scope afe to the trigger level, right?
<Degi>
(Uhm what scope is this circuit for anyway? I'm designing it for 10 GHz BW right now)
<electronic_eel>
I think azonenberg wanted to think about dedicated hardware triggers from the 250mhz one onwards
<electronic_eel>
but I think that all depends on the price such a thing costs
<Degi>
I mean for 250 MHz we could use somewhat cheaper components I think
<Degi>
It should cost about 60 € for the 10 GHz variant. Maybe a bit more.
<Degi>
Like the comparator is 40 € for the cheap version
<electronic_eel>
the HMC674 is quite a fast and expensive part
<Degi>
And outputs 380 mV
<electronic_eel>
maybe start with something cheaper, but still PECL
<Degi>
Idk I dont care about PECL
<electronic_eel>
so to have the same kind of interface
<Degi>
Something with higher swing would be neat
<Degi>
As you can see, I used a transformer and biased the input transistor a little bit that the signal can be easily detected. A higher swing would make the transformer unnecessary
<Degi>
Also we could use actual logic elements instead of transistor resistor logic lol
<electronic_eel>
I think the idea behind these outputs is that they are differential and you should use the differential signal and not a single one
<electronic_eel>
so maybe look for pecl logic elements?
<Degi>
Yes differentially feed it into the transformer and use the single ended signal that comes out of it heh
<electronic_eel>
they have some weird fast logic gates you won't find anywhere else
<Degi>
Heh that thing
<Degi>
Hm why dont most electronics places not list their parts
<Degi>
Not even octopart
<electronic_eel>
I think it is a specialty market and they don't have the volume to get a listing on digikey or similar
<electronic_eel>
as a manufacturer it is quite expensive to get listed there
<Degi>
Oh
<Degi>
Hm could we use JK flip flops instead of SR flip flops?
<electronic_eel>
and they eat lot's of your margin
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<electronic_eel>
the jk flipflop needs a clock signal to change it's state, so I think it is less suited to something where we want to capture an async signal
<electronic_eel>
never heard of these companies though, so they are probably smaller ones
<Degi>
And they dont seem to carry PO74G112A either
<Degi>
Somehow that potatosemi website looks pretty ugly...
<Degi>
How do they manage to keep afloat? Do some big companies buy their parts in large amounts?
<electronic_eel>
I don't know much about their business model. it does not seem to include a budget for web design...
<electronic_eel>
I guess there is a niche market for such ics and devices. when you look at the webpages of their distributors, they also have lot's of specialty electronics
<electronic_eel>
now the jk flipflop you posted, it has pre and clr inputs - that is basically the same as set and reset
<electronic_eel>
it is quite cheap, didn't expect that
<Degi>
Like if we add some 500 MHz comparator...
<Degi>
Page 15 shows the measuring
<Degi>
It gets a start pulse and a stop pulse
<Degi>
Hm the signals need to be 10 ns wide, so an external latch would be needed if the comparator is faster than 100 MHz
<electronic_eel>
the fast comparators also tend to have pecl, cml or lvds outputs, so you'd need to convert that to cmos for the input, after stretching it with the latch
<bvernoux>
A funny or not so funny things
<bvernoux>
for prod done recently
<Degi>
If we add a DAC to the scope and PCIe, that could be used as an audio card...
<bvernoux>
as it seems Isopropyl alcool is "rare"
<bvernoux>
PCB are not cleaned at end of fab
<Degi>
Lol
<bvernoux>
and issue because of micro solder ball are crazy ;)
<Degi>
Like stray unattached solder balls?
<bvernoux>
solution clean the PCB with isopropyl alcool
<bvernoux>
yes
<Degi>
Lol
<bvernoux>
it is 1st time I see that
<electronic_eel>
mhh, isn't pcb production cleaning usually done with a special dishwasher like machine?
<bvernoux>
yes
<electronic_eel>
or sometimes in ultrasonic?
<bvernoux>
they shall clean to avoid residues & micro solder balls for that
<electronic_eel>
I've just seen isopropyl cleaning for small scale cleaning, like rework
<Degi>
Hm you can reuse the isopropyl, right?
<bvernoux>
I have 3L here ;)
<bvernoux>
for that purpose
<bvernoux>
to clean PCB and sensitive electronic things
<Degi>
Hm I have that and somewhat dirty acetone...
<electronic_eel>
Degi: I think in some industrial setup for bigger production runs you probably could, but I think it get's very expensive because of the explosion danger of the vapors. so they tend to use water based solutions there
<Degi>
Hmh
<electronic_eel>
for small scale useage it is not worth to recycle it, it is usually cheap
<electronic_eel>
it is not "usually" right now of course
<Degi>
But on an industrial scale setup I think you can just distill it
<electronic_eel>
yes, but you have to be careful that your whole cleaner and destiller dosn't blow up
<bvernoux>
So far I have 20% defect ;)
<bvernoux>
Symptom no USB DFU and clock does not run
<electronic_eel>
wow, that is a lot of stray solder balls.
<Degi>
Try cleaning with isopropyl and hydrochloric acid, then DI water
<Degi>
How long do we need to sample a signal with 16 bits?
<Degi>
Octopart is listing ADC resolution in BYTES?
<Degi>
Yes, one with >= 2 Bytes thanksl ol
<electronic_eel>
azonenberg: I'm right now looking at your afe design in pcbnew. the first thing that catches my eye is how small the power traces on layer 3 are
<Degi>
Are they 1.5 mm?
<Degi>
*0.15
<electronic_eel>
they look like 0.25mm to me
<electronic_eel>
doesn't that add unnecessary resistance and inductance?
<electronic_eel>
there seems to be lot's of space on that layer
<Degi>
Hm kinda thought about that before, but was too lazy to check and hoped they were bigger... But yes, a bit more like 1.5 mm would be neat
<Degi>
On the PCIe thing I used 1.8 mm
<electronic_eel>
1.5mm wouldn't fit everywhere, but something in the order of 0.8mm or 1mm should be possible. also more vias to connect to it
<electronic_eel>
maybe increasing those is one of the later steps in azonenbergs layout and review cycle
<Degi>
Hmm how do I reset a high side capacitor voltage...
<Degi>
Why can I search nowhere for ADCs by sample window or bandwidth...
<Degi>
Something with bandwidth 100 MHz would be neat, even if it only has 1 MS/s
<electronic_eel>
azonenberg: also looked at your layout of the tps54227. there seem to be some differences to the recommended layout in the datasheet
<electronic_eel>
my experience is that sticking exactly to the vendor datasheet regarding the layout of switchers is highly recommended
<Degi>
Hm do sample and hold amplifiers make sense or should we stick the ADC straight onto the capacitor...
<electronic_eel>
Degi: I think any somewhat fast adc is not that high impedance and needs to sink some charge for it's sampling to work. so there should be some kind of buffer in between
<electronic_eel>
be it a sample and hold or a regular opamp or whatever
<Degi>
I mean sample and hold has lower BW than the ADC lol
<Degi>
I cant find SH above 3 MHz (300 ns sample time)
<electronic_eel>
maybe using a separate s&h got out of fashion and is now usually included into the adc?
<electronic_eel>
I never used a discrete one
<Degi>
Hm I think I can just stick an op amp
<electronic_eel>
azonenberg: also the layout for the lt3042s seem to differ from the datasheet recommendations. now the layout isn't that critical for an ldo, but I think to really profit from the lt3042 the layout has to be carefully considered too
<Degi>
Huh the transistor discharges the cap at 476 µV/µs... Up to 30 mV/µs if the datasheet is to be believeed with 10 µA leakage (though that is at max rated voltage 15 V, while my design only uses 10 V)
<Degi>
We could hook a second HMCAD to the capacitor...
<Degi>
Lol the german mouser page of IC categories is sorted by the english name but displays the german name... Like "Aktive Filter; Verstärker-ICs; Audio-ICs"
<electronic_eel>
I don't understand why they bother translating at all
<Degi>
At least the ADCs are in bits not bytes
<Degi>
I dont either
<electronic_eel>
it adds all kinds of confustion
<Degi>
Yes
<electronic_eel>
sometimes the search doesn't display the correct results because some stupid geolocation thing decides that I want german search results and can't find t
<electronic_eel>
the english term
<Degi>
Yes
<Degi>
Hm I can switch to english... nice
<electronic_eel>
probably you have to allow them some to set some cookies to store the setting
<electronic_eel>
yeah, that would make a nice adc for a scope. like 2 channel 10gsps 8bit and 2 channels of those for example
<Degi>
I mean it has 3 GS/s 14 bit
<Degi>
Thats more bits than my multimeter (which only has a few S/s)
<Degi>
Multimeter costs like 3 bucks per S/s and this thing is like 0.00005 cents per S/s
<bvernoux>
AD9208 is amazing but the price 1832USD/unit ....
<Degi>
Can we have a peltier on the ADC? Maybe we can overclock it lol
<azonenberg>
electronic_eel: i haven't done pours on the power layer yet
<electronic_eel>
at 1832 per adc (you want multiple channels, don't you?), I think you can think about watercooling or cryo-cooling...
<azonenberg>
these traces are just to make it netlist complete
<electronic_eel>
azonenberg: ah, you use directed pours instead of bigger traces
<azonenberg>
Yes. But i'm also going to re-route a bunch of the traces too
<azonenberg>
if you look at the commit message i said something to the effect of "done except for design review and power plane layout" :)
<electronic_eel>
ok, didn't look at the commit messages :)
<azonenberg>
plane layout isnt super critical for this design anyway, because all of the RF is adjacent to layer 2 which is solid ground
<electronic_eel>
yes, of course
<azonenberg>
but for PDN reasons i'm going to obviously use all available space on the layer
<azonenberg>
even if not needed for a ref plane
<azonenberg>
as far as smps/ldo layout goes, i've never had problems from not following the exact layout. Generally it's more following good practices. keeping the switch node short, caps near the input, etc
<electronic_eel>
for example for the switcher they recommend not to put the gnd feedback onto a via, but to route it to the switcher on the top layer
<electronic_eel>
stuff like that can have an influence
<electronic_eel>
so my way to do it usually is not use a finished dcdc module, but individual switchers and then follow the layout guidelines of the ds exactly
<electronic_eel>
has worked quite well in the past
<electronic_eel>
now for the chinese switchers you often have to come up with your own layout, but they tend to be simpler designs where it is not that critical
<electronic_eel>
I like to use SY8113 for example for simple requirements and that has worked out quite well so far
<electronic_eel>
but in this design we aim for higher performance noise wise, and non-optimal layout often results in more noise or worse regulation
<electronic_eel>
there is some good advice especially about switcher layout
<bvernoux>
Does anyone have bought a Rigol MSO5000 ?
<bvernoux>
as for the price < 1KEuros it can be hacked up to 350MHz BW with 8GS/S
<azonenberg>
in particular the bit about vias on the ground doesn't make a lot of sense. Is there any physics rationale for that?
<bvernoux>
I'm pretty sure it can have a BW > 500MHz in fact
<Degi>
Huh thats kinda cheap for 8 GS...
<electronic_eel>
bvernoux: I heard about lot's of sw bugs in the first revisions, don't know if they have fixed those
<azonenberg>
there's nothing remotely sensitive under/near it
<Degi>
HMCAD has 650 MHz BW, we could parallel 8 lol
<azonenberg>
Those return currents are all off in their own little world
<bvernoux>
electronic_eel, Yes I saw that in video tons of SW bugs especially during review more than 1year ago
<azonenberg>
Most layout guidelines i've seen that say "vias bad" are assuming a 2-layer board with very long distances between things. And massive vias that crowd out other stuff
<azonenberg>
meanwhile, i will probably go via-in-pad on the final AFE board for ultimate performance. You literally can't get better parasitics than that
<Degi>
Is there something like a kicad fill but for vias
<Degi>
Oof
<Degi>
Pricy PCB... No more 2€/boardp robably lol
<azonenberg>
Degi: at my usual chinese fab it's 150 USD premium for a prototype volume order and... i think an extra 100/m^2 for volume
<Degi>
For tented vias?
<azonenberg>
for epoxy filled and plated flat s
<azonenberg>
so you cant even tell they're there
<azonenberg>
given how many of these AFEs you could fit on a square meter of pcb you're talking maaaaybe a dollar extra per board
<Degi>
Ah tented via is soldermask lol
<azonenberg>
A board with well over 100 USD of components on it
<Degi>
Hmm okay
<electronic_eel>
azonenberg: referring to what is your " the bit about vias on the ground" comment? in the ti datasheet for the switcher?
<Degi>
Whatever, just high prototype costs...
<azonenberg>
so <1% marginal cost increase
<azonenberg>
electronic_eel: i was more talking about the recommendations to separate PGND and SGND etc too
<electronic_eel>
ah, if you have high return currents flowing in one direction, the current could for example affect your feedback
<azonenberg>
yes, but look at the actual current loops
<azonenberg>
the main high freq loop is from SW through the inductor, then back into ground via the capacitors, then up into the switcher through the ground plane
<azonenberg>
the feedback doesnt get close to that
<azonenberg>
in fact it's on the opposite side of the chip
<electronic_eel>
hmm ok
<azonenberg>
The ground via for the feedback is all the way down near TP21
<azonenberg>
I'm not saying my design is flawless, i'm trying to argue why i did it the way i did based on physics rather than magic
<azonenberg>
If you have a physics-based argument as to why i'm wrong, i'd love to see it :)
<azonenberg>
then the input capacitors are on the left side with the high freq cap super close (might rotate 90 deg and bring it even closer on the side)
<Degi>
Separating power from signal ground would prevent inducing some EMI on the signal paths... Not sure if that matters tbh
<azonenberg>
the bigger 1210 caps cover lower frequency so your losses from moving them a bit further away are insignificant, they're a tiny fraction of a lambda away
* awygle
agrees with azonenberg, ground splits are rarely good
<azonenberg>
Degi: ~all of our signals are differential and on the top layer
<Degi>
Welp then who cares
* awygle
also didn't read the backlog too carefully
<azonenberg>
the only stuff on the back side, next to the power layer, is the spi buses and other slow stuff
<Degi>
I usually see RF devices where the µC and frontend have a split ground inbetween
<azonenberg>
Degi: split grounds are a crutch for bad layout engineers
<azonenberg>
they can save a bad layout but won't help a good one
<Degi>
Welp
<azonenberg>
if you designed the board right you wouldnt have digital return currents messing with the analog signals anyway
<awygle>
the only times they matter are if you have low-frequency noise way across the board from the power input. and even then, barely.
<azonenberg>
and the split wouldn't help
<awygle>
now. do i want all my test equipment on my main lab network, or off on a separate network accessed by a different NIC on my lab server?
<Degi>
*Gives public IP to lab devices*
<electronic_eel>
awygle: I have a separated network for my test gear
<awygle>
Degi: if i could get a big IPv6 block for the price it _should_ cost, i'd do that :p
<electronic_eel>
mainly for security reasons
<miek>
my lab gear lives on its own vlan, with very narrow firewall rules from the main lan
<Degi>
I know a bunch of people who have blocks a few billion IPs big lol
* Degi
doesn't have any lab gear modern enough for LAN
<Degi>
GPIB anyone?
<azonenberg>
i wont buy test eq without a lan interface :p
<azonenberg>
I keep mine on a dedicated "lab scada" network
* awygle
wonders if these units speak DHCP
<electronic_eel>
Degi: how about GPIB to lan adapters?
<miek>
my most expensive bit of kit runs win2k :(
<miek>
that's going nowhere near the internet
<azonenberg>
my "research/workstation" network has ~unrestricted access to it, but all other vlans, including but not limited to "wifi for wife's laptop and game consoles etc", can't touch it
<azonenberg>
miek: yeah my lecroy scopes run win7 right now
* awygle
abruptly remembers he was working before his new managed switch arrived
<azonenberg>
they are able to be upgraded to win10 but i dont see the need to pay for that
<Degi>
Lol
<azonenberg>
like, they already have a plaintext scpi interface, if i let an untrusted machine talk to that i'm screwed
<azonenberg>
so how do potential windows vulns increase my attack surface?
<Degi>
Is that something like a root console?
<azonenberg>
arbitrary control of the instrument including arbitrary vbscript plus changing any setting you can from the front panel
<Degi>
I see
<electronic_eel>
often you can upload new firmware through the lan interface or scpi
<Degi>
Also my GPIB scope is broke
<miek>
looking for scpi on shodan is .. alarming
<Degi>
I mean at least our scope can run a firewall too I guess...
<azonenberg>
it's like worrying about a machine with an unauthenticated telnet console having an old OS
<azonenberg>
exploiting an os bug is by far the hardest way to own it
<Degi>
Hm I only get 13 results on shodan?
<azonenberg>
I assume any test equipment i buy will execute arbitrary commands from anyone who can send packets to it, then design the network with that in mind
<Degi>
Is it a bad idea to put telnet onto a laser on my wifi network?
<azonenberg>
i think i'm up to 13 vlans at home
* Degi
wonders about a SSH to UART interface on a ESP8266
<azonenberg>
vlan 2, one of two that are bridged to wifi, basically can't route anywhere but the internet :p
<Degi>
At university, our computers get public IPs
<azonenberg>
i mean i have public ipv6 addresses across most of my network too
<azonenberg>
doesnt mean i have wide open firewall rules
<Degi>
IPv4 tho
<awygle>
the thrilling conclusion of the DHCP saga - the Rigol does, the Siglent doesn't say, and the CyberPower does
<awygle>
also, the CyberPower is cool as hell and I should have bought the 24-port version
<azonenberg>
awygle: i like static ips on anything that hosts a server
<azonenberg>
because i want it to stay put
<awygle>
i both want it to stay put and want DHCP to work
<azonenberg>
i only use dhcp on client machines that i sit in front of and don't ever talk to from outside
<awygle>
so i handle the "stay put" on the DHCP server side
<azonenberg>
and honestly, even then i use statics most of the time
<azonenberg>
i mean i have to track all of my boxen in DNS anyway
<awygle>
i want to be able to plug in and _go_
<awygle>
and make it nice later
* azonenberg
has a 100+ line dns zone file for his house
<awygle>
this rack could use a patch panel and a bigger PDU
<awygle>
Next Time (TM)
<awygle>
OK the siglent does support it, sweet
<electronic_eel>
awygle: should have bought the 24 port version? what version did you buy?
<awygle>
8
<electronic_eel>
urgh
<electronic_eel>
I consider 48 ports reasonable for a one person appartement
<electronic_eel>
or do you have lot's of dedicated switches for each network instead of vlans?
<azonenberg>
electronic_eel: for me and my wife in our house, i have a cisco nexus 3064 (48x 10G + 4x 40G) as the core switch and four catalyst 2970Gs (24x 1G copper + 4x 1G optic, soon to be replaced with something with 10G uplinks)
<Degi>
Meanwhile I have 7 ports ;(
<awygle>
no, i got the 8-port PDU
<awygle>
8-socket?
<azonenberg>
i have 4x cat5e + 4x OM4 to every bedroom, every bench in the lab, both workstations in the office, the media area of the living room, etc
<awygle>
i also got an 8-port Ethernet managed switch to run the equipment network, which is an adjunct to my 48-port Cisco switch
<electronic_eel>
azonenberg: that's more like it for a nice home
<azonenberg>
i'm still filling out all the conduit and laying fiber in the tray but when i'm done it's going to be something over 2km of cable
<azonenberg>
my desk has four 3/4" conduits to it and a 12" cable tray terminating in the ceiling
<electronic_eel>
I just have 10g between server, main workstation and lab pc
<awygle>
but 8 plugs is not enough, esp. given the cool features this thing has
<electronic_eel>
1g everywhere else
<azonenberg>
the box i'm sitting in front of now has 2x 10G + 2x 40G NICs, and i couldn't find MPO keystones
<azonenberg>
so i'm provisioning four LCs for each 40G link
<azonenberg>
and just pulling duplex fibers
<azonenberg>
Or i guess i could run some of the 40G-over-duplex-fiber CWDM sfps
<azonenberg>
qsfps*
<azonenberg>
so far i dont have any 40G in service although i have the nics for it, because the cable plant isn't there. my desk is fed by a single duplex LC fiber hooked to a 10g nic and the 10g core switch , just haphazardly tossed in the cable tray because it's not the irght length for the actual run
<azonenberg>
and i havent had time to measure the correct length and order the right fiber
bvernoux has quit [Quit: Leaving]
<electronic_eel>
did you rent a fusion splicer to install the fiber or do you buy preconfigured fiber in the correct lengths?
<azonenberg>
I bought preterminated from FS
<azonenberg>
each room has a separate parallel 3/4" conduit for copper and fiber, which then drops into a 12" cable tray in the ceiling of the first floor/basement that provides the backhaul routing to the switch rack in the lab
<azonenberg>
i pull the cat5 first, leave a decent bit of service loop, read the foot markings on the cable, and then order multimode in the same length
<azonenberg>
while the paths aren't quite exactly the same length if i have a few feet of service loop that makes up for it
<azonenberg>
The service loops in that part of the tray started getting out of hand and i began pulling subsequent cables in the opposite direction, with service loops where they exited the tray, rather than trying to put all of them over the switch rack. Which just wasn't going to work
<azonenberg>
Shipment update... the PMK stuff came in. It's exactly what i wanted, and leaves me zero doubt that i have been using pmk accessories all along (not that there was much doubt to begin with)
<azonenberg>
I also got a probe shell from shapeways printed in "premium versatile plastic", one of their cheaper SLS nylon materials
<Degi>
Nice cable management
<Degi>
Also lol at the conduits which look like shower hoses
<azonenberg>
It's unusable, the cavity that the probe PCB goes into is clogged
<azonenberg>
Degi: those aren't conduit, it's Type MC (metal clad) cable
<Degi>
How does a probe get clogged
<Degi>
Too many electrons?
<azonenberg>
it's a prefab flexible aluminum armor over conductors
<azonenberg>
you cut to length, strip off the jacket, then terminate the conductors
<azonenberg>
no pull involved, but you can only have one circuit in it
<Degi>
We have wool cables (maybe with asbestos)
<azonenberg>
i use it for all of my in-wall wiring as well as in-tray power circuits because it's much less work than pulling three separate conductors and a conduit
<azonenberg>
and compared to plastic jacketed cables is more fire resistant and much less susceptible to mechanical damage
<azonenberg>
and no the mechancial enclosure of the probe is solid plastic
<azonenberg>
there's no slit down the middle for the board to go into
<azonenberg>
whatever process they use to clean out the unsintered powder didnt work
<azonenberg>
when i poke at it with a knife blade toward the ends, i can see loose nylon powder
<azonenberg>
So basically this process does not handle high aspect ratio holes well
<Degi>
Maybe add isopropyl
<azonenberg>
or slits
<azonenberg>
you know how rare that stuff is these days? :p
<Degi>
Lol should I send you some
<azonenberg>
more seriously, though, i am not going to clean each and every probe shell i order. It's not cost effective or practical
<azonenberg>
not when the shapeways MJF process can handle this exact same geometry just fine
<azonenberg>
i ordered shells in a range of materials to see which worked and which did not
<azonenberg>
This one does not
<azonenberg>
Not a problem as far as the project as a whole is concerned, just an FYI that this is not the process to use next time i need something with similar shape
<Degi>
Woo print them with a resin printer
<azonenberg>
The MJF process, which is also selective sintering, handles this same part fine
<azonenberg>
maybe the "versatile" process is stickier or something, idk
<azonenberg>
MJF glass filled nylon is currently my preferred material for probe shells. it was the first one i tried and i liked it
<azonenberg>
i'm just seeing what other fish are in the sea