00:48 <mtrbot-ml> [mattermost] <astro> zynq eth startup reliability really has degraded in the current codebase :(

00:52 <mtrbot-ml> [mattermost] <sb10q> timing related problem? now the code is executing from SDRAM while initializing Ethernet

00:52 <mtrbot-ml> [mattermost] <sb10q> so the execution speed is different

01:09 <mtrbot-ml> [mattermost] <astro> cold reboots help

01:09 <mtrbot-ml> [mattermost] <astro> that's an idea

01:10 <mtrbot-ml> [mattermost] <astro> but there shouldn't be anything timing sensitive in the eth driver

01:10 <mtrbot-ml> [mattermost] <astro> especially since there wasn't even a timer until very few days ago

01:14 <mtrbot-ml> [mattermost] <sb10q> could be a race condition between the cpu writing the registers and something in the hardware

19:48 <stroboko1p> hi, has anyone looked into https://github.com/m-labs/nmigen/issues/325 yet? I struck it again so I'm investigating a bit

19:48 <stroboko1p> I think it happens when a Signal is assigned from a Signal inside an Array of Signals, and another Signal selects which one

19:51 <stroboko1p> look at this statement for example: (switch (cat (slice (sig s_sel) 3:4)) (case 1 (eq (slice (sig bus__dat_r) 24:32) (proxy (array [(slice (sig Reg0x40_o_port) 24:32), (slice (sig Reg0x44_o_port) 24:32)]) (sig s_target)))))

19:54 <stroboko1p> I'm digging around in python not knowing how nmigen works, but I think what I see is this: a switch, then the only case 1, then an "eq" with this structure:

19:55 <stroboko1p> (eq target array[val0,val1] sel)

19:58 <stroboko1p> and then this is what rtlil.py works on, right? now that's too deep for me right now, but this is what seems to result from the assignment:

20:01 <stroboko1p> (in the rtlil output file) switch sel ; case 1'0 ; assign target val0 ; case 1'- ; assign target val1 ; end

20:03 <stroboko1p> in the Verilog output the case 1'- becomes case 2'h?:

20:13 <stroboko1p> mhh now I wonder if the case 1'- is RTLIL's way of defining the Verilog "default:" or VHDL "when others =>" case, and yosys doesn't handle it correctly, or if nmigen generates wrong RTLIL