10:10 <sb0> key2: https://twitter.com/fpga_dave/status/1125310556989161472

10:11 <sb0> key2: minerva does 27.36 MHz only (https://nixbld.m-labs.hk/build/3731/log)

10:13 <key2> sb0: I guess it has some critical path that need to be broken

10:13 <key2> but with an artix we go at 100mhz

10:15 <key2> jfng1 is the one who knows why I guess :)

11:05 <daveshah> key2/sb0: this is using the ECP5-5G which is the fastest grade. If you are using a non-5G ECP5, note that nextpnr defaults to speed grade 6 which is slowest. If it's something like a non-5G Versa, then adding --speed 8 will get better timings

11:06 <daveshah> Also that looks like quite an old nextpnr version (before HeAP), newer nextpnr has better timing and much faster runtimes

11:07 <daveshah> I think part of the problem is a lack of ECP5 DSP inference in Yosys (which is on the todo list)

14:36 <sb0> daveshah: indeed - that new placer is much faster

14:36 <sb0> slightly better timing after the upgrade too. 31.89MHz.

14:41 <sb0> and 41.63 with --speed 8

14:49 <key2> still far from the 81 tho

14:50 <sb0> with 5g it's 48.51

14:51 <daveshah> Make sure Yosys is up to date too, there have been a few new optimisations recently (and slightly more useful net names)

14:57 <sb0> aha! without multiplier it's 77.72 MHz

14:58 <sb0> and in the slower designs the slack histogram show that it's a minority of nets that slow down the design

14:58 <sb0> key2: 81?

14:59 <key2> mhz

14:59 <sb0> the litex design is 75, not 81

14:59 <key2> ahh

14:59 <key2> multiplicator has been added recently

14:59 <key2> and it does a simple ' * ' in verilog

15:00 <key2> (contrary to the divisor