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[artiq] sbourdeauducq commented on issue #1126: Could be the compiler getting slow for some reason; try using the usual Python profiling tools, and minimizing it by removing the core device interaction (e.g. like ``artiq_compile``). https://github.com/m-labs/artiq/issues/1126#issuecomment-410909669
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Because the divider has the option for nearly arbitrary phase adjustment, the stop condition can arrive when the pulse stream is a Logic 1 and create a runt pulse.
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[artiq] hartytp commented on issue #1080: @gkasprow can you remind me, do you have any boards that show these ARTIQ PRBS errors? There isn't any point debugging on boards that don't show them. https://github.com/m-labs/artiq/issues/1080#issuecomment-410948013
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[artiq] hartytp commented on issue #1080: If it's not the input buffer, then it's got to be something like the routing of the clock to the transceiver, transceiver settings, JESD stack, etc. I think that to chase that down, we really need to look at the JESD lanes with a fast probe. @gkasprow can you have a look at that, please? Maybe trigger your scope from the HMC7043 output. https://github.com/m-labs/art
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[artiq] hartytp commented on issue #1080: Yes. But at least this way we know that the input stage is good as I assume that's common. Anything after it needs to be looked at separately by looking on the transceiver pin.... https://github.com/m-labs/artiq/issues/1080#issuecomment-410951429
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[artiq] whitequark closed issue #1107: Setting a dataset in a try/except block on the core device fails to compile in 3.6 https://github.com/m-labs/artiq/issues/1107
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[artiq] enjoy-digital commented on issue #1127: @sbourdeauducq: that's probably better to restart the jesd after a prbs test indeed. (spi reset and jesd core reset as you are doing). https://github.com/m-labs/artiq/issues/1127#issuecomment-410964708
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[artiq] enjoy-digital commented on issue #1127: I'm not saying it's a workaround. I just don't know how the DAC is exiting the PRBS mode, so don't know is STPL is supposed to work after that. On the JESD core, exiting the PRBS mode should be clean, since it does not really impact the core itself, we are just injecting prbs datas when PRBS is enabled and then get back to JESD core datas when disabled. I only se
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[artiq] enjoy-digital commented on issue #1127: I'm not saying it's a workaround. I just don't know how the DAC is exiting the PRBS mode, so don't know if STPL is supposed to work after that. On the JESD core, exiting the PRBS mode should be clean, since it does not really impact the core itself, we are just injecting prbs datas when PRBS is enabled and then get back to JESD core datas when disabled. I only se
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[artiq] hartytp commented on issue #1080: @gkasprow how many boards do you have? how many exhibit PRBS issues? If not all boards exhibit this, does it depend on the AMC or the RTM, or some combination of the two (i.e. can you run the tests with different combinations of AMC and RTMs). Also, on the boards that fail, do they always fail? Or, are there some which only fail sometimes? https://github.com/m-labs/
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[artiq] sbourdeauducq commented on issue #1080: > If not all boards exhibit this, does it depend on the AMC or the RTM, or some combination of the two (i.e. can you run the tests with different combinations of AMC and RTMs).... https://github.com/m-labs/artiq/issues/1080#issuecomment-410975809
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[artiq] gkasprow commented on issue #1080: AFAIR it was RTM that causes the PRBS problem. I will check it today. I'm formally on holidays until end of September (overdue leave) but without everyday dose of electronics life gets boring. https://github.com/m-labs/artiq/issues/1080#issuecomment-410977357
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[artiq] hartytp commented on issue #1080: > AFAIR it was RTM that causes the PRBS problem. I will check it today. I'm formally on holidays until end of September (overdue leave) but without everyday dose of electronics life gets boring.... https://github.com/m-labs/artiq/issues/1080#issuecomment-410978437
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[artiq] enjoy-digital commented on issue #1127: I'm saying that i don't know if the DAC can work correctly after a PRBS test without reset, so if you want to avoid a reset, then we need to be sure what can be expected from the DAC. (but from my understanding since the DAC will detect the JESD stream is missing when PRBS is sent, i expect it to require another link establishment to get back to JESD data). ht
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[artiq] klickverbot commented on issue #1126: (And removing `count()` will cause the kernel to return early, whereas with it in, it needs to wait for the RTIO timeline to reach the current cursor.) https://github.com/m-labs/artiq/issues/1126#issuecomment-411015698
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artiq/release-3 df23224 Robert Jördens: browser: handle windows file urls for feeding h5py...
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[artiq] jordens commented on issue #965: I have seen this (the state being NULL bytes) as well after a blue screen on windows. It would be great if we could work around windows file system limitations by just keeping one previous version of the file around, e.g. the one that was last successfully used to restore the state on dashboard/browser start. https://github.com/m-labs/artiq/issues/965#issuecomment-41
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[artiq] gkasprow commented on issue #1080: I didn't said that it works with CLK1. it was pure coincidence, maybe they broadcasted something else on FM when we did tests a few months ago :) https://github.com/m-labs/artiq/issues/1080#issuecomment-411048654
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[artiq] hartytp commented on issue #1080: @gkasprow to make sure we don't waste time, please can you send me the binaries you were using for your tests? I'd like to check that I can reproduce the PRBS issues on my board with your binaries. If I can then I'll post it back to you tomorrow morning. https://github.com/m-labs/artiq/issues/1080#issuecomment-411172564
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