sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<GitHub-m-labs> [artiq] prasath-d opened issue #1096: Urukul AD9910 ref clk mismatch https://github.com/m-labs/artiq/issues/1096
<GitHub-m-labs> [artiq] jordens commented on issue #1096: Please provide some context. What is your reference clock, how is the board populated, how is it connected, and what's the reference frequency? See the documentation for info on the fields and arguments. https://github.com/m-labs/artiq/issues/1096#issuecomment-402621440
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1055: What's are you writing to register 0x71? Are you setting bit 4, 2 & 1? https://github.com/m-labs/artiq/issues/1055#issuecomment-402624430
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<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: Well, you have the code... we're not touching 0x71. https://github.com/m-labs/artiq/issues/1055#issuecomment-402626651
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<sb0> larsc, do you have contacts with people who designed the HMC7043? this chip is really annoying and we could use some review by someone who knows all the quirks ...
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1055: Anyway there is no change:... https://github.com/m-labs/artiq/issues/1055#issuecomment-402629780
<GitHub-m-labs> [artiq] hartytp commented on issue #1055: @enjoy-digital When I looked at this, I tried setting some bits in 0x71 (see top level post) but it didn't seem to make any difference. Maybe there is something else that needs doing?... https://github.com/m-labs/artiq/issues/1055#issuecomment-402630015
<larsc> sb0: I know the person. But you can ask him directly, he replies in https://ez.analog.com/community/clock_and_timing
<GitHub-m-labs> [artiq] hartytp commented on issue #1080: @gkasprow what's the timeline for looking at the SI for the two GTP_CLK{1,2} inputs on the AMC FPGA, as well as the SYSREF input? https://github.com/m-labs/artiq/issues/1080#issuecomment-402631975
<GitHub-m-labs> [artiq] prasath-d commented on issue #1096: Kasli is flashed with Tester variant.... https://github.com/m-labs/artiq/issues/1096#issuecomment-402633750
<GitHub-m-labs> [artiq] enjoy-digital commented on issue #1055: What are you writing to register 0x71? Are you setting bits 4, 2 & 1? https://github.com/m-labs/artiq/issues/1055#issuecomment-402624430
<GitHub-m-labs> [artiq] jordens commented on issue #1096: How is the clocking circuitry on the board populated, how is it connected? How do you actually want to clock it? https://github.com/m-labs/artiq/issues/1096#issuecomment-402638052
<GitHub-m-labs> [artiq] prasath-d commented on issue #1096: The Clock to the Urukul is managed by Kasli and I didn't populate anything other than EEM connectors.... https://github.com/m-labs/artiq/issues/1096#issuecomment-402643820
<GitHub-m-labs> [migen] enjoy-digital pushed 1 new commit to master: https://github.com/m-labs/migen/commit/b515b0e82fe89536535eb6be4a64ca418fa04e74
<GitHub-m-labs> migen/master b515b0e Florent Kermarrec: platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs
<bb-m-labs> build #295 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/295
<GitHub-m-labs> [artiq] sbourdeauducq commented on issue #1080: @hartytp Also: it it only the standalone target that is affected by this crazy problem? What happens with masterdac and satellite? https://github.com/m-labs/artiq/issues/1080#issuecomment-402669620
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<GitHub-m-labs> [artiq] hartytp commented on issue #1080: Will check later today using the masterdac. https://github.com/m-labs/artiq/issues/1080#issuecomment-402677877
<GitHub-m-labs> [artiq] sbourdeauducq commented on commit 4eb26c0: Good catch. Seems inter-board sync is working a bit better, though I could only test it a few times due to https://github.com/sinara-hw/sinara/issues/567. https://github.com/m-labs/artiq/commit/4eb26c00503333e90112a3d800229809bfddaae8#commitcomment-29604418
<sb0> are there two (or more) possible synchronization states for the same SYSREF phase?
<sb0> can you get into such a state by varying the SYSREF phase with the DAC operating?
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<sb0> does anyone has, or knows where to get, 2HP blank panels e.g. 30849-001?
<sb0> they seem to be available only at distrelec.de, and they are expensive + with some annoying export problems
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<GitHub-m-labs> [artiq] jordens commented on issue #1096: Are you using the on board 100 MHz oscillator or the kasli 125 MHz clock via mmcx? See the schematic for the clocking circuit and the board population. https://github.com/m-labs/artiq/issues/1096#issuecomment-402780929
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<omid> rjo, sb0: From the NIST CLOCK table here https://m-labs.hk/artiq/manual-release-3/core_device.html how do I find where say TTL3 is located on my KC705 board? I didn't find my answer looking at the board manual.
<rjo> omid: nist clock is (as the name says) a NIST clock hardware adapter. it's an FMC backplane. you'll have to ask the nist folks for the schematic.
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<d_n|a> Are there any known issues with sync_struct reliability? I'm making heavy use of `append` mods (which I've fixed and exposed to the core device in my local tree), but applets sporadically fail to receive some of the dataset updates
<d_n|a> (The applets in question are subscribing over a socket to the master rather than via IPC/the dashboard, for … reasons)
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<GitHub-m-labs> [artiq] philipkent opened issue #1097: Unable to building target binaries using the artiq-dev package on Linux https://github.com/m-labs/artiq/issues/1097
<GitHub-m-labs> [artiq] philipkent commented on issue #1097: If it helps, I am on the release-3 branch of the artiq source from github. After creating the artiq-dev conda environment using:... https://github.com/m-labs/artiq/issues/1097#issuecomment-402869475
<GitHub-m-labs> [artiq] philipkent commented on issue #1097: The ultimate goal of this is to expand the output FIFO depth to 1024 which we need to avoid underflow errors when the FIFO fills up. https://github.com/m-labs/artiq/issues/1097#issuecomment-402871810
<cr1901_modern> sb0: Why do you prefer the style of FSM that Migen generates as opposed to something "simpler", like: https://www.altera.com/support/support-resources/design-examples/design-software/verilog/ver_statem.html? Better timing closure in your method?
<cr1901_modern> I know your way is the "correct" way to do it, but I never actually knew why.