<GitHub66>
[smoltcp] phil-opp commented on pull request #57 b8e109c: I changed `TxToken::consume` to also return a `Result<R>`, but I think it's still better to keep the `junk` buffer. The reason is that a packet drop on send should be transparent to the sender and not return an `Err`. https://git.io/vFI9I
<GitHub16>
[smoltcp] phil-opp commented on pull request #57 b8e109c: I implemented it https://git.io/vFI9L
<shuffle2>
hrm how does FSM operate wrt clock domains?
<whitequark>
FSM is a syntactic sugar for some signals
<shuffle2>
i dont really get how you drive a clock domain
<shuffle2>
will at least cause the sync.spi stuff to be exersized, altho of course it doesn't behave the way the spi clk should at all
<shuffle2>
how do people do this?
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<shuffle2>
how do you index a constant with a signal?
<shuffle2>
using Memory also seems to make migen unhappy, yay
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<shuffle2>
(it was because i hadn't assigned the Memory instance to module.specials, and was trying to index at the bit level, which apparently you can't do)
<sb0>
shuffle2, if you're doing a SPI receiver you may want not to use the provided clock for anything other than data transfer
<sb0>
since it's potentially not free-running and typically slow
<sb0>
also, note that slow clocks (i.e. with slow rising edges) may need to be filtered when entering less-slow logic like a FPGA, otherwise any noise during the edge may result in additional unwanted cycles and obscure bugs in your design
<shuffle2>
it was already working fine with my verilog impl...but i've changed my design already just to make migen work
<shuffle2>
the project is very much a hack (ie it just needs to work "most of the time")
<shuffle2>
s.chip_id[s.byte_pos - 1][s.bit_pos] (or w/e) does not
<sb0>
and you need 8 bits on the other memory port, i.e. you have asymmetric ports?
<shuffle2>
not sure what you mean
<sb0>
why not make your memory data 1-bit wide?
<shuffle2>
that is to fetch a bit for spi SO signal
<sb0>
instead of 8
<shuffle2>
because i wrongly assumed about how i could index it, i guess :)
<sb0>
indexing by Signal works, but you have to use Array
<sb0>
but then you have two "muxes" instead of one. a 1-bit memory is a simpler structure.
<sb0>
if you don't need to access 8-bit at a time somewhere else, then 1-bit is enough
<shuffle2>
ok, i was worried it would change how the synth is able to map it to bram (for the main memory, not this chip_id one)
<shuffle2>
i need to be able to use a lot of bram
<sb0>
iirc the synthesizer handles 1-bit BRAMs just fine
<cr1901_modern>
two muxes?
<shuffle2>
sb0: fwiw, making it 1bit wide doesn't change the error i was having
<sb0>
what error?
<shuffle2>
and 8bit seems to work fine so w/e
<shuffle2>
basically if i set width to 1, it still just acts the same as if it were 8
<sb0>
"it"=?
<shuffle2>
the memory
<sb0>
no it doesn't
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<GitHub152>
[smoltcp] pothos commented on issue #65: Good idea, there was one more problem I could spot through the tests: When it continued to send data, it was using a wrong (too low) sequence number.... https://git.io/vFLLy
<shuffle2>
sb0: probably issue was that i was not using synthesizable Memory? when i try to .build(), migen complains that it can't handle _MemoryLocation type
<shuffle2>
maybe there is some behavorial difference? anyway...another thing there are no docs about...actually using Memory in synth :(
<shuffle2>
does it mean you can't actually synth things like "m = Memory(..,init=[1]); x = m[0]
<shuffle2>
"?
<shuffle2>
ie can't use inferred style and instead need to manually use signals returned from get_port?
<cr1901_modern>
You need to use the signals returned from get_port() for memorys to work.
<shuffle2>
what is the point of supporting indexing the Memory object then