sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
<GitHub> [artiq] whitequark commented on issue #700: @sbourdeauducq This is not a bug per se, rather this is how I understood the specification.... https://github.com/m-labs/artiq/issues/700#issuecomment-290883785
<GitHub> [artiq] whitequark commented on issue #700: @sbourdeauducq This is not a bug per se, rather this is how I understood the specification.... https://github.com/m-labs/artiq/issues/700#issuecomment-290883785
<GitHub> [artiq] sbourdeauducq commented on issue #700: > Do I understand it right that replay should advance the timeline?... https://github.com/m-labs/artiq/issues/700#issuecomment-290889168
<sb0> whitequark, why is an API needed? if the MSBs are 0 then don't write them.
<sb0> this is generally how RTIO deals with large data
<sb0> anyway, small detail, getting this stuff to work without this optimization would be good already ...
<sb0> what's the current status?
<whitequark> sb0: that's just more complexity in the firmware
<whitequark> I get u32's from the kernel, I write them...
<whitequark> the status is exactly as before
<sb0> whitequark, that's also making the dma sequence shorter and uses memory bandwidth more efficiently for short writes.
<sb0> so it's a valid optimization, but luxury considering the current status.
<whitequark> sb0: ok. let me fix the timeline advance issue. but i don't know what to do with the other one.
<sb0> whitequark, where does it freeze? have you replaced the arbiter already?
<whitequark> no, I haven't replaced the arbiter, I don't see why that is going to change anything
<sb0> try it
<whitequark> also I don't really know how to replace it
<sb0> I wanted to replace it anyway
<whitequark> that part of code is pretty obscure
<sb0> so, if it's obscure, how do you know it's not going to change anything?
<sb0> does it still freeze waiting for arb_gnt?
<whitequark> the logic is not obscure. what's obscure is the organization
<sb0> you need to add a CSR to CSRSwitch, then map it to the kernel CPU
<whitequark> as for where it freezes, let me instrument it again on master
<whitequark> I haven't considered that changing the DMA BAR is broken
<whitequark> or that it even could be broken
<whitequark> but that does fit the symptoms
<sb0> not completely, I got it to crap out with just replay() as well
<whitequark> hm
<whitequark> ah yes, I had that at some point, but it stopped being reproducible
<GitHub53> [migen] sbourdeauducq pushed 1 new commit to master: https://git.io/vSWiZ
<GitHub53> migen/master ca3cde6 Sebastien Bourdeauducq: use math.gcd instead of deprecated fractions.gcd
<sb0> whitequark, so, what is preventing you from replacing the arbiter right now?
<whitequark> nothing except the fact that I really dislike the idea of getting into that mess
<bb-m-labs> build #139 of migen is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/migen/builds/139
<whitequark> but sure. I should do it.
<GitHub> [artiq] sbourdeauducq pushed 1 new commit to master: https://github.com/m-labs/artiq/commit/0a687b7902c4fb0f27ce2c7fa63bc0b7bde9cf92
<GitHub> artiq/master 0a687b7 Sebastien Bourdeauducq: drtio: report satellite errors through firmware
<bb-m-labs> build #497 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/497 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<bb-m-labs> build #1433 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1433 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> ^ this was a revision where rpc time was ok at 2ms. let's see if it's really the network...
<sb0> bb-m-labs, force build artiq
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #498 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/498
<bb-m-labs> build #1434 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1434
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #499 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/499
<bb-m-labs> build #1435 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1435
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<cr1901_modern> sb0: Somehow I just learned about the EDIF backend (I prob knew it existed at some point). I'm trying it out/learning about EDIF at the same time. What does this error mean: https://github.com/m-labs/migen/blob/master/migen/fhdl/edif.py#L200
<cr1901_modern> Okay, I think I see... all I/O has to be done via Instance classes. This is going to be very weird generating Migen => EDIF plus UCF => IceStorm
<sb0> cr1901_modern, what is weird about it? all a EDIF file is is blackboxes connected together. Instances fit perfectly.
<sb0> whitequark, do you know why conda sometimes fails with "fatal: destination path '/var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/conda-bld/artiq-kc705-nist_clock_1491023827445/work' already exists and is not an empty directory."
<sb0> this is what is happening right now
<sb0> whitequark, well, for the "sometimes" part, it turns out conda leaves a ton of rubbish in /var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/conda-bld, and sometimes the new rubbish conflicts with the old
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> bb-m-labs, force build artiq
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<GitHub> [artiq] sbourdeauducq opened issue #701: conda leaves build files around https://github.com/m-labs/artiq/issues/701
<sb0> whitequark, also, if DMA still hangs after replacing the arbiter - have you looked at the states of the FSMs?
<bb-m-labs> build #500 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/500
<bb-m-labs> build #1436 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1436
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #501 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/501
<bb-m-labs> build #1437 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1437
<sb0> fuck
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<sb0> why did that break, work again, and break again?
<GitHub> [artiq] sbourdeauducq commented on issue #701: Deleting all this trash before a build isn't always enough to prevent the error, so there is another obscure conda problem here. https://github.com/m-labs/artiq/issues/701#issuecomment-290917896
<bb-m-labs> build #502 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/502
<bb-m-labs> build #1438 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1438
<sb0> why did that break, work again, and break again?
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build forced [ETA 39m27s]
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<sb0> bb-m-labs, force build --revision=0cda1a3d3415a2ca7109c9a2ffb5ce6844ca4ad9 artiq
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<sb0> fuck this shit
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> The build has been queued, I'll give a shout when it starts
<bb-m-labs> build #503 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/503
<bb-m-labs> build #1439 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1439
<bb-m-labs> build forced [ETA 39m27s]
<bb-m-labs> I'll give a shout when the build finishes
<bb-m-labs> build #504 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/504
<bb-m-labs> build #1440 of artiq is complete: Failure [failed] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1440
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<cr1901_modern> sb0: I thought the edif backend could be used to bypass verilog generation completely as an input to yosys and friends
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<GitHub> [artiq] tballance commented on issue #585: I have drafted a conda recipe for a simple stripped down version of artiq which includes (entry points for) only those bits needed on 'remote' rpc servers:... https://github.com/m-labs/artiq/issues/585#issuecomment-290953656