04:17 <sb0> another problem with ddma is handling the analyzer

09:09 <cr1901_modern> _florent_: Does Arty support FT245 mode (i.e. are the correct pins wired to the FPGA)? Some jackass decided to omit the page with the USB connections from the official schematic.

10:48 <cr1901_modern> sb0: Been thinking again (I know bad idea). Are you willing to elaborate on the highlighted: https://irclog.whitequark.org/m-labs/2016-10-31#18065049;

11:25 <_florent_> cr1901_modern: no Arty does not support FT245 mode. The FTDI chip is only here for UART and JTAG.

11:30 <cr1901_modern> great... the only board I know of that supports FT245 is minispartan. So I guess that's a blessing in disguise even if the DRAM is borked.

11:50 <whitequark> sb0: still working on this. bisecting LLVM involves a *lot* of compilation.

15:53 <GitHub85> [artiq] sbourdeauducq pushed 1 new commit to master: https://git.io/vX4Xm

15:53 <GitHub85> artiq/master 453e8b7 Sebastien Bourdeauducq: runtime: support configurations without moninj, log or dds

16:15 <bb-m-labs> build #163 of artiq-board is complete: Success [build successful] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/163

16:20 <bb-m-labs> build #1061 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/1061 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>