sb0 changed the topic of #m-labs to: ARTIQ, Migen, MiSoC, Mixxeo & other M-Labs projects :: fka #milkymist :: Logs http://irclog.whitequark.org/m-labs
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<cr1901_modern>
sb0: I wish to add little-endian CSRs. I think the easiest way to do this is to add a new member to _CSRBase that allows a user to specify the endianness. >>
<cr1901_modern>
Anything that subclasses _CompoundCSR should do something like: if self.endianness = LITTLE, for i in range(nwords) else for i in reversed(range(nwords))
<cr1901_modern>
Does that sound good?
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<cr1901_modern>
Scratch part of that. I shouldn't need to add anything to _CSRBase, since CSR regs are 8 bits.
<sb0>
cr1901_modern, what do you need LE for?
<sb0>
this whole LE/BE problem is a waste of time
<cr1901_modern>
I want to use Migen for other projects besides LM32/Milkymist. If I can almost fully replace Verilog for writing synthesizable code, that would make my life easier
<cr1901_modern>
Why do you think it's a waste of time?
<cr1901_modern>
Yes, of course I can just make my own custom register bus if you don't want me to screw with CSRs. Just though I'd try avoiding reinventing the wheel
<cr1901_modern>
sb0: I think I get where you're coming from. CSR is meant to be primarily used for MiGen/MiSoc-related projects only, correct?
<sb0>
no, it's because every feature added is a liability
<sb0>
have to maintain it, makes the code complex and harder to read, may break when other features are added, provides hiding space for bugs, etc.
<cr1901_modern>
Okay, then. I'll use LE for my own personal projects then. Not a big deal.
<cr1901_modern>
(i.e. I'll just make my own personal module for it)
<sb0>
why not have the software functions access the CSR bus in BE?
<sb0>
CSR is slow anyway, the LE->BE conversion won't actually make any difference since the CPU itself is splitting the transfers into 8-bit chunks
<cr1901_modern>
B/c the CPU in question is one of the only CPUs I can think of that's still produced with an 8-bit external data bus AND supports 16-bit xfers
<cr1901_modern>
I didn't think of that
<sb0>
you can also use a 16-bit CSR bus. or wishbone.
<cr1901_modern>
"CPU itself is splitting the transfers into 8-bit chunks" <== Again, I didn't think of that. My fault.
<sb0>
maybe the C code of the access functions could even be the same for LE and BE CPUs....
<cr1901_modern>
It's not difficult to write endian-independent code
<cr1901_modern>
I do a lot of vintage work- for fun/hobby. So let's get that out of the way before ppl make fun of me. >>
<cr1901_modern>
The CPU in question that I wanted to interface is a 6502 variant that can do 16-bit xfers. 6502 is a little-endian processor, 8-bit external bus. So that was the use case
<cr1901_modern>
I'm not trying to justify what I was trying to do- just explaining my thought process. :P
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<GitHub63>
[artiq] sbourdeauducq pushed 2 new commits to master: http://git.io/vTTva
<GitHub63>
artiq/master d8917fd Sebastien Bourdeauducq: Merge branch 'master' of github.com:m-labs/artiq
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<sb0>
oh, pyqtgraph comes with docking that does pretty much what i want
<cr1901_modern>
Automated data slicing... that's cool
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<sb0>
sturmflut2, you said your emmc working correctly with the android kernel. is that with or without debug_quirks2?
<sb0>
also, did you have the wifi enabled? I suspect some "intel storage cluster" bug that could manifest itself when both the emmc and wifi are in use...
<sb0>
kernels that don't have the emmc bug coincidentally have a sdio bug that makes the wifi driver not recognize the card
<sb0>
and I had the emmc bug kick in once right when I was inserting a sd card. could be a coincidence, but who knows....
<sb0>
those overengineered intel systems are a royal pita